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Safety-Critical ISO 26262 Hardware Development
OneSpin and Austemper Design at DAC

OneSpin and Austemper: Joint Presentation on HW Development Flow for Safety-Critical Applications

What: Daily presentations on hardware development flow for safety-critical applications

When: Daily, June 25–27, at the 55th Design Automation Conference (DAC)

Where: OneSpin's exhibit booth (Moscone West 2nd Floor, booth #2611)

Duration: 30 minutes + Q&A

Cost: Free to attend; advanced registration required

Topic and Speakers


Fault-tolerant hardware is the backbone of many safety-critical systems for automotive, medical, and aerospace applications. Safety mechanisms detect random hardware faults and raise alarms that can save lives. Alas, they also increase the complexity and cost of your hardware design and verification. In addition to their usual tasks, engineers need to ensure that hardware will detect a huge number of potential faults that could happen in the field.

OneSpin Solutions and Austemper Design Systems have teamed up to produce this hands‑on presentation that demonstrates a highly automated design and verification flow addressing key challenges in your development of hardware with integrated safety mechanisms.

Key Takeaways

1.    Automatic insertion of hardware safety mechanisms in your RTL module

2.    Automatic, exhaustive verification that the RTL still functions correctly and that safety mechanisms are adequate to meet ISO 26262 and related standards

3.    Fault simulation and formal together to verify that your large SoC meets safety goals

Who should attend?

Managers, architects, designers, and verification engineers involved in the development of fault-tolerant, digital hardware for automotive, medical, aerospace, and other safety-critical applications.

Jörg Große, Product Manager Functional Safety, OneSpin Solutions

Jörg Große is the product manager for functional safety at OneSpin Solutions GmbH. He has more than 20 years of experience in electronic design automation (EDA), functional verification, and ASIC design, having served at companies in Europe, the United States, and New Zealand.

As co-founder of a successful Silicon Valley-based startup, Jörg was central in developing the concept of fault/mutation testing into a state-of-the-art EDA tool. He deployed this technology in many leading semiconductor companies, increasing the quality of their functional verification.

In his latest role at OneSpin, Jörg is applying formal verification technology to create a new set of EDA tools to address tough functional safety challenges at the ASIC level. Jörg holds a Diplom-Ingenieur (FH) in electrical engineering from Anhalt University of Applied Sciences in Germany. 

Sanjay Pillay, Founder and CEO, Austemper Design

Sanjay has 22 years of experience in management and engineering in enterprise, automotive, and consumer SoC development. He founded Austemper in March 2015 to address the need for a complete, automated, scalable safety engineering tool set, which he had found to be lacking.

In various roles throughout his career, Sanjay has championed and developed advanced methodologies and flows to improve accuracy, productivity, and predictability in ASIC development. Prior to founding Austemper, he headed the worldwide enterprise SSD controller SoC development at HGST/STEC, where he also set up the Austin design center. Sanjay has also served as a functional safety consultant. Sanjay led the SoC architecture and worldwide SoC development organizations at Trident/NXP/Conexant, delivering the most power-efficient STB SoC. He was the head of Audio ASIC development at Maxim. Sanjay was head of ASIC development for DSP and embedded products at Cirrus Logic, delivering high volume products to tier-1 customers. Prior to that, he held engineering roles spanning the entire development flow at Cirrus Logic, working on consumer and automotive products. His first engineering job was at Ross Technology, a startup developing high performance SPARC Processors.

Sanjay's drive for continuous improvement has resulted in inventions in circuit design, power management, signal processing, and algorithms, with 12 issued and multiple pending patents. He has a BTech in electrical engineering from the Indian Institute of Technology, New Delhi, India and an MS in electrical engineering from Clemson University, Clemson, SC.

Reserve your seat today!

This presentation is free to attend, but space is extremely limited—sign up now to avoid disappointment! Indicate your preferred presentation date and time below and we will do our best to place you in your desired slot. You will receive an email confirming the date and time no later than one week prior to DAC.

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