DVCon US 2021
Register Online | Virtual Event | March 1-4 2021
DVCon United States 2021
DVCon brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications, and demonstrations for the practical use of EDA solutions for electronic design.
OneSpin is excited to partner with DVCon as an exhibitor and workshop contributor. Find our exhibitor information here.
On Monday, March 1st at 9:00 - 10:00 PST, OneSpin's John Hallman will join Jean-Philippe Martin & Brent Sherman of Intel to host the workshop, "Getting To Know Accellera’s Emerging Hardware Security Standard: Security Annotation For Electronic Design Integration"
ABSTRACT:
"This session will introduce an emerging new standard called Security Annotation for Electronic Design Integration (SA-EDI) to address security concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to provide information about the IP security relevant to the integrator and recommended mitigations to implement and risk to address. At the conclusion of this session, attendees will better understand risks associated with IP and become familiar with the SA-EDI standard, including how it can be applied and when it will be available for reference."
On Thursday, March 4th at 13:30 - 14:30 PST, OneSpin's Nicolae Tusinschi will host the workshop, "Beyond Bug Hunting: Verification Coverage From Safety To Certification."
ABSTRACT:
"This workshop will explore how mutation analysis can have a positive impact on the safety of your design and provide the signoff confidence needed to achieve proper safety certification. In addition, the workshop will show how to achieve a meaningful integration of formal and simulation coverage metrics. A long-standing wish of many verification engineers and managers, coverage integration reduces effort overlap between simulation and formal and enables faster, more rigorous signoff."
On Thursday, March 4th at 13:00 PST, OneSpin Application Engineers Martin Rowe & Sasa Stamekovic will host a Sponsored Engagement session "AMA with OneSpin Engineers" -
Ask your question for our AEs ahead of the event: Submit Question
Event Details
Date:
March 1-4
Time
Program begins: Mar. 1 9:00 PST
Program ends: Mar. 4 2:30 PST
About The Event Host
The Design and Verification Conference (DVCon) is the leading event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.
