Making Sure RISC-V Designs Work As Expected
By Ann Steffora-Mutschler, Semiconductor Engineering
The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips.
[…]
Others agree. “Only formal can exhaustively analyze designs and provide the absence of bugs,” said Tom Anderson, a member of OneSpin Solutions’ technical marketing team. “Formal equivalence checking also verifies the implementation flow and ensures that no hardware Trojans are inserted into the design. There is strong interest in using formal to verify open-source RISC-V cores in particular due to the multiplicity of suppliers and design variations. This verification should be performed with third-party tools so that core integrators can re-run the same analysis as the core providers.”
