Join OneSpin at DVCon US 2018!
We're looking forward to catching up with lovers of formal verification from Silicon Valley and around the world at DVCon US!
Join us at the DoubleTree Hotel in San Jose, February 26th through March 1st, 2018, where the following events will offer opportunities to see OneSpin's formal verification experts in action:
Wednesday, February 28 | 3:00–4:30 PM | Oak
Speaker: Sasa Stamenkovic, OneSpin Solutions
Authors: Sasa Stamenkovic, Sven Beyer, and Sergio Marchese (OneSpin); Ravi Ram, Adam Elkins, and Adnan Pratama (Xilinx)
Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats is not sufficient for the target application, floating-point hardware might be required. Unfortunately, floating-point units are complex to design, and notoriously challenging to verify. Since the famous 1994 Intel Pentium bug, many companies have investigated and successfully applied formal methods to this task. However, solutions often rely on a mix of the following: hard-to-use formal tools; highly specialized engineering skills; availability of a suitable executable model of the hardware; significant, design-specific engineering effort. In this paper, we present an alternative floating-point hardware verification approach based on a reusable, IEEE 754 compliant SystemVerilog arithmetic library. While not addressing all verification challenges, this method enables engineers to setup a formal testbench and uncover deep corner case bugs with minimal effort. Results from industrial applications are reported.
Thursday, March 1 | 2:00–3:30 PM | Sierra
Speakers: Muhammad Haque Khan and Vladislav Palfy, OneSpin Solutions
Organizer: Tom Anderson, OneSpin Solutions
Modern verification methodologies incorporate multiple coverage solutions. These range from functional to structural coverage, leverage various coverage models and operate using varied technologies in both the simulation and formal process. The main purpose of these coverage solutions is to establish a signoff metric that indicates when enough verification has been performed. However, as coverage approaches have evolved, new use models have emerged for these tools that increases their value in the verification process. The ability of these tools to provide guidance to areas insufficiently tested, or uncover buggy scenarios is still being explored, to great effect. Mutation coverage is a relatively new technique pioneered by formal and simulation providers.
The workshop agenda will consist of:
- Introduction to mutation coverage techniques
- Mutation coverage with formal – it’s not so tough!
- Sign-off with mutation coverage
- Overview of bug hunting techniques with formal
- Bug hunting using mutation coverage
- Bug hunting on a practical design example
- Overview of potential improvements using this technique.
Exhibit Floor, Booth 902
Monday, February 26 | 5:00–7:00 PM
Tuesday, February 27 | 2:30–6:00 PM
Wednesday, February 28 | 5:00–7:00 PM
Stop by booth 902 to talk with our team about how our formal verification solutions can help you to meet your coverage goals.
Contact us for DVCon US
If you’ll be in San Jose for DVCon US and would like to meet with our team, please leave us a message here.