Join OneSpin users and experts for our first ever users' group!

OneSpin is growing, and we are proud to announce the launch of our first ever users' group event, Osmosis. This all-day event centers on knowledge transfer among our IC integrity experts and our users and will culminate in a traditional Bavarian dinner in a festive setting. 

Highlights:

• Keynote on IC Integrity from OneSpin's President and CEO Raik Brinkmann
• Technical deep-dives on:
  • Functional Correctness
  • Safety
  • Security
  • RISC-V
• Presentations from OneSpin users detailing their design successes
• Face time with our Product Managers in focused small group discussions at lunchtime
• SnApp Notes Live and AMA (Ask Me Anything): interactive demos and Q&A session with our Application Engineers and Product Managers

Discover the OneSpin users who are going to present at this year's Osmosis event.

Keerthikumara Devarajegowda

Keerthikumara Devarajegowda received his Master’s degree from Technische Universität Kaiserslautern, Germany in the year 2016. He is currently with Infineon Technologies AG and is also pursuing his PhD at Technische Universität Kaiserslautern, Germany under the guidance of Dr. Wolfgang Ecker and Prof. Wolfgang Kunz. His research interests include formal verification, digital design modeling and automation techniques.

Presentation: Processor Verification with Symbolic Quick Error Detection Using Symbolic Initial States: a RISC-V case study

With the increasing complexity of microarchitectures and the growing demand for highly optimized and individually customized processors, for example for Internet of Things (IoT) applications, processor verification is an increasing challenge in SoC design. The manual efforts and verification expertise required are the major hurdles to adaptation of formal techniques for processor verification.

This talk will highlight the application of a formal processor verification technique --- Symbolic Quick Error Detection Using Symbolic Initial States (S²QED) --- on a RISC-V processor core. S²QED is micro-architecture independent and is very powerful in finding hard to find logic bugs in processor pipelines. The approach is highly automated and requires minimal manual effort. The results of the application of the technique on a RISC-V processor core will be discussed.

Antti Rautakoura

SoC/ASIC Verification Specialist and PhD Candidate

Antti Rautakoura is well-versed in verification management, coverage, UVM, formal verification, and emulation platforms. Currently on study leave from Nokia Solutions and Networks to pursue his PhD research around Agile Methods on HW Development, Antti has over ten years of experience with 4G and 5G ASICs with the likes of Nokia Mobile and Renesas Electronics.

Presentation: Coverage Planning and Verification Management

Jürgen Dennerlein

November 2007 to January 2014
Product Development and Manufacturing of Monitoring and Diagnostic System Components; Senior Hardware Developer; Group Head;
Framatome GmbH, Erlangen, Germany

Since February 2014
Product Development; I&C Hardware Development Expert; Platform Architect
Framatome GmbH, Erlangen, Germany

Current Projects: Mechanical Equipment, HPD based Compact Safety Controller, Analog Signal Conditioning

Presentation: Equivalence Checking in the V&V of FPGAs for Nuclear Applications

Let us know if you would like to attend our first user group meeting in Munich and we will come back to you with a confirmation: