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DVClub Europe: Formal Verification Adoption Made Easy

FREE to attend Online | Virtual Event | September 7, 2021

 

DVClub Europe September 2021

Formal Verification Adoption Made Easy

OneSpin: A Siemens Business is excited to partner with DVClub Europe as an annual sponsor and session presenter. 

At 12:55 BST, Product Specialist for SystemC Vlada Kalinic will present Formal for Easing the SystemC/C++ Verification Burden

ABSTRACT: 

The use of high-level synthesis (HLS) has substantial benefits in terms of flexibility and time-to-market. HLS transforms algorithmic and potentially untimed design models, often written in SystemC and C++, to fully timed RTL design blocks. But as you raise the abstraction level of your design, it becomes more natural to also raise the level of the verification. At the pre-HLS algorithmic level, verifying the design directly against its specification with less concern for coding detail is a requirement. However, the verification options for SystemC and C++ designs have not kept pace with the synthesis technology. Due to the limited availability of SystemC tools, much of the verification task is performed on the resulting synthesized RTL code, introducing a level of indirection that makes correcting issues at the SystemC/C++ level complex and time consuming. Specific issues related to this abstract design level may be easily tackled with the right formal verification environment. We’ll show you how automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis.

Learn more: DVClub Europe September Event Website

Event Details

Date: 

September 7, 2021 

Time

Program runs: 12:00 - 13:30 BST

About the Event Host

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.

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