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EDACentrum: RISC-V Activities Workshop

December 2, 2021 | Virtual Event


This joint academic/industry workshop aims to stimulate the exchange of information among the attendees about already existing or planned RISC-V activities. The workshop provides a platform for how these activities can be extended across projects or to develop innovative ideas, activities, and collaborations. This workshop has been initiated by the BMBF funded projects SAFE4I and Scale4Edge and will be executed in conjunction with the edaWorkshop21.

We will have two invited keynote talks for the topic "Towards Trustworthy RISC-V Processors for Safety-Critical Applications"

RISC-V is one of the hottest trends in the industry these days, with its mature software toolchain and many hardware processor providers offering implementations ranging from textbook open-source cores to high-end commercial ones. The freedom to configure and customize the RISC-V ISA in accordance to the system needs, including custom instructions, is one of its strongest appeals, making custom RISC-V CPUs an attractive choice for an unprecedented number of companies. However, the challenge of actually designing a RISC-V core with custom extensions and ensuring its correct functional behaviour is still significant, even more in environments with high safety and security expectations. In this session, we present an automated flow to generate RISC-V cores with custom extensions together with their complete verification.


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