2014-06-01 - 2014-06-05
51st Design Automation Conference
Moscone Center, San Francisco, CA
June 1st to 5th, 2014
OneSpin Booth #1219
At the Design Automation Conference (DAC) this year, OneSpin will be exhibiting at booth 1219 and will have multiple suites available for private demos of our latest technologies, see below.
If you would be interested in some of the new technologies we will be demonstrating, or simply meeting with the executives and technologists who will be at the show, please let us know your areaas of interest and the best times and days to meet, by emailing us at firstname.lastname@example.org
Panels and Designer Track Presentations
OneSpin is sponsoring a Pavilion panel this year “The Asymptote of Verification” on June 2 at 5:15 p.m. in the Pavilion (Booth #313). The panel will feature three top verification experts including Holger Busch of Infineon Technologies, a long-time expert on the OneSpin formal tools.
Holger will also present “Formal Safety Verification With Qualified Property Sets” during the Designer Track Session “Accelerating Productivity Through Formal and Static Methods” on June 3 at 4pm, and repeat this presentation on the OneSpin booth once a day.
OneSpin will have five demonstrations available in our suites, and can also tailor presentations and demonstrations to your interests and needs. Our major areas of focus are:
Safety Critical Design Solutions
Employing formal verification to provide the most rigorous verification environments possible, to adhere to industry standards on safety. This application based demonstration will show how standards such as ISO 26262 may be applied in practice using formal techniques, including the verification of failsafe design structures and fault testing.
Inspect Automated Verification for Designers
Providing in-depth analysis of design code at the push of a button with no need to write assertions. Using powerful formal techniques and assertion synthesis, together with Sequential RTL Analysis, we will demonstrate how many difficult problems may be eliminated early on while reducing the requirement for extensive simulation and test bench writing.
Verify Coverage-Driven, Assertion-Based Verification
Our latest Quantify Observation Coverage technology will be demonstrated in a full Assertion-Based Verification closed loop flow. This solution allows for precise coverage guidance to track every corner case and difficult test scenario, as well as bring together formal and simulation –based techniques. Also included are pre-packaged verification solutions such as automated X-propagation analysis, connectivity and register testing, VIP, etc.
Advanced Sequential Equivalency Checking for FPGA
Our Sequential Equivalency Checking technology, already used by many synthesis vendors to check their flow, is now being leveraged in the FPGA world to save significant amount of time during the FPGA implementation / debug loop, while providing an order of magnitude acceleration for the debug of implementation problems. The OneSpin EC product is the only solution available that can handle unique FPGA optimizations.
General Overview OneSpin Formal based Solutions
We can also provide a complete overview of the entire OneSpin formal based product line, from automated solutions, through advanced coverage driven assertion verification, to equivalency checking, and discuss the application of this technology to your verification problems.
To sign up for any of these demos, or for a more general meeting with the technologists or executives that will be at the show, please email us with times and dates that would suit you, and your areas of interest, to email@example.com