DVCon China 2018
Shanghai, China | April 18, 2018
Meet our verification experts at the upcoming DVCon China in Shanghai-Pudong, China!
1:00 to 1:30 PM | Room 2A
Modern verification methodologies incorporate multiple coverage solutions. These range from functional to structural coverage, leverage various coverage models and operate using varied technologies in both the simulation and formal process. The main purpose of these coverage solutions is to establish a signoff metric that indicates when enough verification has been performed. However, as coverage approaches have evolved, new use models have emerged for these tools that increases their value in the verification process. The ability of these tools to provide guidance to areas insufficiently tested, or uncover buggy scenarios is still being explored, to great effect. Mutation coverage is a relatively new technique pioneered by formal and simulation providers.
5:00 to 6:00 PM | Foyer
The use of SystemC/C++ system models significantly increases the productivity of hardware design flows. SystemC/C++ source code is more compact than RTL, simulates faster, and can target a wide range of microarchitectures, depending on performance, area and timing requirements. On the functional verification front, due to a lack of tools and methodologies benefits are less evident. Top-level test vectors used to validate behavioral model provide limited coverage. Failures are hard to debug. Verification of the generated RTL code comes late in the development process and is not efficient. This paper shows how automated formal verification solutions well established in RTL development, once adapted and extended to analyze and verify SystemC/C++ code prior to high-level synthesis, provide a much needed boost to verification quality and productivity. Experiences in industrial applications are reported.