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In the news

A Holistic View Of RISC-V Verification

By Nicolae Tusinschi, Product Specialist Design Verification, OneSpin

Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles published, conference talks presented, and upcoming talks accepted. We tend to focus on the challenges of verifying RISC-V IP cores and system-on-chip (SoC) designs containing these cores. Since I have been on the front line speaking at many of these conferences, I’d like to share my perspective on how the industry’s view of RISC-V verification is growing and evolving.

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Are Digital Twins Something For EDA To Pursue? - Part one: Defining the digital twins concept; the trouble with models; the issue with the ecosystem.

By Ann Steffora Mutschler, Semiconductor Engineering | Featuring Raik Brinkmann, President and CEO of OneSpin

‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing the implementation usage using data run safely in virtual and FPGA based prototyping?

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Podcast: Swimming in the SoC

By Amelia Dalton, EE Journal | Feat. Rob van Blommestein, Head of Marketing, OneSpin

In this week’s episode of Fish Fry, we are swimming in SoCs! Randy Fish (UltraSoC) joins us to discuss the deep waters of embedded analytics and AI platform debug. Ramsay Allen (Moortec) and I chat about the rising tide of advanced chip node designs and the benefits of in-chip monitoring IP. Finally, Rob van Blommestein (OneSpin) and sail through the choppy waters of IC verification.

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Hardware-Software Co-Design Reappears

By Brian Bailey, Semiconductor Engineering | Featuring Tom Anderson, Technical Marketing, OneSpin

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on.

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Partitioning Drives Architectural Considerations - Experts at the Table, part 3: Systems of subsystems; heterogeneous systems; re-partitioning

By Ann Steffora Mutschler, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing, OneSpin

Semiconductor Engineering sat down to discuss partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical marketing consultant at OneSpin; and Drew Wingard, CTO at Sonics [Sonics was acquired by Facebook in March 2019]. What follows are excerpts of that discussion.

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Breaking Down the Debug Process | Experts at the Table, Part 2

By Brian Bailey, Semiconductor Engineering | Feat. Dominik Strasser, VP Engineering, OneSpin

Semiconductor Engineering sat down to discuss debugging complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions.

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Tackling Safety And Security

By Brian Bailey, Semiconductor Engineering | Featuring David Landoll, Solutions Architect, OneSpin

Experts at the Table: Who is responsible for safety and security and what can we do as an industry to make it better?

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauman, vice president of engineering for Tortuga Logic; and Mike Bartley, chief executive officer for TV&S. This is the third part of this discussion.


Landoll: I hear that in DO-254 all the time. There is a push and pull that a lot of people doing implementations know that the energy being spent is not energy to make it safer, it is energy to get the compliance signed off. If I could put the energy into doing something else, I could actually make it safer. But I am not allowed to do that because it won’t be approved.

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HW/SW Design At The Intelligent Edge

By Ann Steffora Mutschler, Semiconductor Engineering | Featuring Raik Brinkmann, President and CEO, OneSpin

Systems are extremely specific and power-constrained, which makes design extremely complex.

Adding intelligence to the edge is a lot more difficult than it might first appear, because it requires an understanding of what gets processed where based on assumptions about what the edge actually will look like over time.


“When you build systems, there are multiple things you need to care for,” said Raik Brinkman, CEO of OneSpin Solutions. “It’s the same whether you do it in hardware or software, but the challenge is how you keep track of data. Nothing is fixed, and as you get new data, you may find you have gaps and have to retrain systems. There are multiple layers of data. And with machine learning, you need to recompute everything. This is a big management task. People are not aware of the complexity in all of this. They’re happy enough that it works.”

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