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In the news

Utilizing More Data to Improve Chip Design

By Ann Steffora Mutschler, Semiconductor Engineering

Different ways of collecting, analyzing and applying that data to improve efficiency and reliability.

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what’s important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly complex chips and reduce the overall time to tapeout.

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New Design Approaches At 7/5nm

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By Ed Sperling, Semiconductor Engineering

The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved.

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Formal Verification Of RISC-V Cores

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By Sven Beyer, Semiconductor Engineering

RISC-V is hot and stands at the beginning of what may be a major shift in the industry. Even a cursory review of upcoming conferences programs and recent technical articles makes that clear. While it is still early in the evolution of the processor architecture, there is certainly the potential that RISC-V will be a game-changer in the IP and semiconductor industry. As “a free and open ISA enabling a new era of processor innovation through open standard collaboration,” it directly challenges several well-established processor families. This definition comes from the RISC-V Foundation, which assumed support and evolution of RISC-V after the original development in the EECS Department at the University of California, Berkeley.

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The Challenge Of RISC-V Compliance

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By Brian Bailey, Semiconductor Engineering

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that claim to be RISC-V have implemented the specification correctly?

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Can Debug Be Tamed?

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By Brian Bailey, Semiconductor Engineering

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time.

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Partitioning Drives Architectural Considerations

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By Ann Steffora-Mutschler, Semiconductor Engineering

Semiconductor Engineering sat down to explore partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; Rod Metcalfe, product management group director in the Digital & Signoff Group at Cadence; Mark Olen, product marketing group manager at Mentor, a Siemens Business; Tom Anderson, technical marketing consultant at OneSpin; and Drew Wingard, CTO at Sonics. What follows are excerpts of that discussion.

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DVCon USA 2019 preview: OneSpin

OneSpin will formally unveil its formal RISC-V Integrity Verification Solution for development and assessment of the open-source IP at DVCon next week (Doubletree Hotel, San Jose, February 25-28). The company is exhibiting at Booth #301. The product will also be on view at EmbeddedWorld in Nuremberg on eVision System's booth (Hall 4, Booth 4-560).

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Using AI Data For Security

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By Ann Steffora-Mutschler, Semiconductor Engineering

Artificial intelligence is migrating from the cloud to IoT edge devices. Now the question is how to apply that same technology to protect data and identify abnormal activity in those devices and the systems connected to them.

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Press Contact

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Nanette Collins
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