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In the news

Seven Steps for IoT Verification

By Tom Anderson, Elektronikpraxis

Many IoT devices are complex system-on-chip (SoC) designs with embedded software. The development isn't trivial, and the verification is critical for successful deployments in end products.

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The Impact Of Domain Crossing On Safety

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By Brian Bailey, Semiconductor Engineering

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications engineering, scientist for Synopsys. Part one can be found here. Part two is here. What follows are excerpts of that discussion.

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The Impact Of Moore’s Law Ending

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By Brian Bailey, Semiconductor Engineering

Over the past couple of process nodes the chip industry has come to grips with the fact that Moore’s Law is slowing down or ending for many market segments. What isn’t clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity.

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EDA Cloud Adoption Hits Speed Bumps

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By Brian Bailey, Semiconductor Engineering

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If moving semiconductor design to the Cloud was easy and beneficial, everyone would be doing it. But so far, few have done more than dip a toe. The level of difficulty associated with migrating to the Cloud varies, depending upon who you talk to. The reality is that not everyone makes it as easy as it could be, or is not willing to put the necessary effort into making it easier. There is certainly a chicken-and-egg problem.

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Integrating Results And Coverage From Simulation And Formal

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By Tom Anderson, Semiconductor Engineering

Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation licenses, and servers. Yet even unlimited simulation capability provided no guarantee of functional correctness. Constrained-random simulation, by its very nature, is probabilistic and has little chance of exercising enough of the design to find deep, corner-case bugs.

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RISC-V: More Than A Core

By Brian Bailey, Semiconductor Engineering

The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V’s success.

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ESD Alliance Workshop on Digital Marketing: Tools and Sales

By Paul McLellan, Cadence Breakfast Bytes Blogs

Yesterday was the first part about the ESD Alliance Digital Marketing workshop. Today, it is part 2 (of 2).

Today's marketers need to be hands-on since there are a lot of different aspects and it is too slow (not agile) to have to use different organizations for everything. Getting from here to there requires training, and there is a lot around. I'm going to skip over a lot of what Nicolas said and jump to his recommendations. Note that these recommendations are for small and medium-sized companies. In a big company, there will almost certainly be a CRM system like Salesforce already in place, and perhaps other tools too.

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11 Myths About Formal Verification

By Tom Anderson, Electronic Design

Formal verification, which uses mathematical analysis rather than simulation tests, has been available in commercial EDA tools for more than 20 years and in academia much longer. As with many new technologies, initial adoption was slow and limited to companies who had in-house formal experts. This has changed dramatically in the last dozen years or so. Almost every chip-development team makes some use of formal tools, and the market continues to grow. Nevertheless, some myths about formal persist, and they may still be deterring some engineers who could benefit from it. It’s time for the truth to be told.

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