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In the news

Verification Planning And Management With Formal

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By Tom Anderson, Semicondutor Engineering

Over the last twenty years, formal verification has grown from a niche technology practiced only by specialists to an essential part of mainstream chip development. Along the way, several advances were needed to make wider adoption of formal feasible.

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Making Sure RISC-V Designs Work As Expected

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By Ann Steffora-Mutschler, Semiconductor Engineering

The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips.

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Securing Chips from the Ground Up

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By Sergio Marchese, Electronic Design

Pre-silicon validation and verification of hardware security requirements are crucial, which pushes the need for more robust, efficient design flows.

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Uses And Limitations Of AI In Chip Design

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By Ed Sperling, Semiconductor Engineering

Raik Brinkmann, president and CEO of OneSpin Solutions, sat down with Semiconductor Engineering to talk about AI changes and challenges, new opportunities for using existing technology to improve AI, and vice versa. What follows are excerpts of that conversation.

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Open Source Hardware Risks

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By Ann Steffora-Mutschler, Semiconductor Engineering

Open-source hardware is gaining attention on a variety of fronts, from chiplets and the underlying infrastructure to the ecosystems required to support open-source and hybrid open-source and proprietary designs.

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Improving Algorithms With High-Level Synthesis

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By Ann Steffora-Mutschler, Semiconductor Engineering

Most computer algorithms today are developed in high-level languages on general-purpose computers. But someday they may be deployed in embedded systems where the development, verification, and validation of algorithms is done in languages like python, Java, C++, or even numerical frameworks like MatLab.

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