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By Ann Steffora Mutschler, Semiconductor Engineering | Feat. Jörg Grosse, Product Manager Functional Safety, OneSpin
Circuit aging was considered somebody else’s problem when most designs were for chips in consumer applications, but not anymore.
Much of this reflects a shift in markets. When most chips were designed for consumer electronics, such as smart phones, designs typically were replaced every couple of years. But with the mobile phone market flattening, and as chips increasingly are used in automotive, industrial and medical applications, reliability has become much more important. Aging is a major component of reliability, and concerns are even starting to spill over to chips designed for mobile phone devices. Numerous industry insiders say mobile phone OEMs are demanding that new chips last at least four years rather than two, and in other markets they may have to remain functional for up to 20 years.
Experts at the Table, part 1: How do automotive notions of safety and security compare to those in avionics?
Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauman, vice president of engineering for Tortuga Logic; and Mike Bartley, chief executive officer for TV&S. What follows are excerpts of that conversation.
Machine learning, with the correct hardware infrastructure, may soon reach endpoints.
Comments by Raik Brinkmann, President and CEO of OneSpin.
Chipmakers are getting ready to debut inference chips for endpoint devices, even though the rest of the machine-learning ecosystem has yet to be established.
Whatever infrastructure does exist today is mostly in the cloud, on edge-computing gateways, or in company-specific data centers, which most companies continue to use. For example, Tesla has its own data center. So do most major carmakers, banks, and virtually every Fortune 1,000 company. And while some processes have been moved into public clouds, the majority of data is staying put for privacy reasons.
Still, something has to be done to handle the mountain of data heading their way
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...“The trend for people doing edge devices is to include multiple levels of AI. So a simple AI algorithm may detect movement, which powers up the next stage, which may switch to recognition. And if that’s interesting, then it will power up the real computation engine that does something.”
By Dr. Raik Brinkmann, President and CEO of OneSpin, for EE Times
Secure enclaves and root of trust are not enough. Hardware vulnerabilities affect the security of automotive, medical, and IoT systems.
In January 2018, computer security researchers disclosed two critical processor vulnerabilities that malicious programs could exploit to leak secure data: Meltdown and Spectre.
The engineering community and the public at large are accustomed to software vulnerabilities requiring frequent app updates or installation of operating system patches. These were different — hardware was the culprit, and hardware is not cheap to update.
The only practical approach is to release new software that, at the cost of making the system slower and less energy efficient, masks vulnerable hardware functions or avoids their use. Meltdown and Spectre sparked a series of investigations into hardware security.
Researchers already unveiled numerous more vulnerabilities, including Foreshadow, ZombieLoad, RIDL, and Fallout. These hardware flaws compromise the security of personal computers, smartphones, and even the cloud.
By John Hallman, Product Manager Trust & Security, OneSpin | Blog for Semiconductor Engineering
As the supply chain of components and IP expands, so too do the opportunities for adversarial tampering.
For those around the microelectronic component industry for many years, we have seen quite a transformation of capability, sourcing of the supply chain, and now threats to these devices that drive the technology in our world today.
These integrated circuits (ICs), once so simple as a few transistors, have continued to follow Moore’s Law and are now made up of tens of billions of transistors. ICs have become so complex that they too are now made up of many independent modules, often referred to as third-party intellectual property (3PIP).
In addition to the increased capability, the source of the components, as well as the 3PIP, has become a global effort. Examples of this globalization are evident by design and production of such major systems as the Apple iPhone and the F-35 fighter jet. The major suppliers for the Apple iPhone all demonstrate a global contribution to a complex supply chain. Similarly, several countries, including the U.S., Netherlands, Norway, Canada, Australia, United Kingdom, Turkey, and Italy, are all source supply for the F-35.
As the complexity of the system, components, and the supply chain all increase, the opportunity for adversarial tampering causes a growing concern.
By Brian Bailey, Semiconductor Engineering | Feat. Tobias Welp, Engineering Manager, OneSpin
Adding an eFPGA into an SoC is more complex than just adding an accelerator.
Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric itself?
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Formal verification can help. “The FPGA fabric must be verified twice, first by the vendor and then by the user programming it,” explains Tobias Welp, engineering manager for OneSpin Solutions. “Formal equivalence checking, a key verification step, is even more important when fabric is involved because FPGA synthesis tools offer advanced optimizations to meet power, performance, and area (PPA) goals. Some of these optimizations change the state space of the design and move logic across register boundaries, so sequential equivalence checking is required. This should be performed in multiple stages to ensure that the input RTL, the post-synthesis netlist, the placed-and-routed netlist, and the programming bitstream are all functionally equivalent.”
By Ann Steffora Mutschler, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, OneSpin
How it is characterized, verified and used can have a big impact on reliability and compatibility in a design.
Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor.
This has been one of the challenges with IP over the years. In many cases, IP is poorly characterized, regardless of whether that IP was commercially or internally developed by a chipmaker. But as chips become more complex, subject to more interactions from multiple power domains and use cases, even the best intentions to characterize IP can go awry.
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Just the term “quality” is overloaded due to associations with “Six Sigma” and other specific industry initiatives, suggested Tom Anderson, technical marketing consultant at OneSpin Solutions. “The term ‘IP integrity’ is broader in scope.”
Assuring the integrity of a design encompasses four critical dimensions—functional correctness, safety, security and trust. Functional correctness is the focus of traditional verification, ensuring that the design meets its functional specification. In the case of IP, this specification often involves a standard such as the USB 3.0 interface or the RISC-V instruction set architecture (ISA).
But functional correctness alone isn’t sufficient for many designs. “Safety-critical applications, such as mil-aero, embedded medical devices and self-driving cars, require that designs operate correctly in the field,” said Anderson. “Random errors such as alpha particle hits must not compromise design safety. Many types of IP are used for these applications, so the providers must account for safety, and the IP integrators must confirm this. In many of these same applications, the IP must not contain security vulnerabilities that could allow malicious actors to take control of chips containing the IP in the field. Both IP providers and IP integrators must screen designs for any accidental security holes.”
OneSpin Solutions' recent launches for Intel FPGAs and RISC-V ISA compliance will be at the forefront of its exhibition presence at the Design Automation Conference next month (read more about them here). The company will also be active in DAC’s Designer Track.
DAC 2019 is to take place at the Las Vegas Convention Center from June 2-6. The exhibition runs June 3-5 and OneSpin will be present at Booth #308.
In addition to demonstrations (which can be booked here), staff will be on hand to discuss recent technical papers and research from the company.
Nicolae Tusinschi, product specialist, design verification , will present, “Unbounded Formal Verification of RISC-V CSRs with Interval Property Checking,” during the Designer Track session on “New Frontiers in Formal and Static Verification” (Monday June 3, 10:30am-12:00pm, Room N262).
During the Designer/IP Track Poster Networking Reception, Sasa Stamenkovic, senior field application engineering, will be available to discuss “Advances in Formal Connectivity Checking –– A Case Study on a Multi-Billion-Gate SoC” (Monday June 3, from 5:00pm).
