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In the news

Is Cloud Computing Suitable For Chip Design?

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Brian Bailey, Semiconductor Engineering

Is semiconductor design being left behind in a cloud-dominated world? Finance, CRM, office applications and many other sectors have made the switch to a cloud-based computing environment, but the EDA industry and its users have hardly started the migration. Are EDA needs and concerns that different from everyone else? We are starting to see announcements from EDA companies, but few cheerleaders are ready to announce that they do design in the cloud.

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AI Chips Must Get The Floating-Point Math Right

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By Sergio Marchese, Semiconductor Engineering

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks today are often based on operations that use multiplication and addition of floating-point values, which subsequently need to be scaled to different sizes and for different needs. Modern FPGAs such as Intel Arria-10 and Xilinx Everest include floating-point units in their DSP slices that can be leveraged to optimize classification, detection, and image recognition tasks. Convolutional neural networks (CNNs) are popular for computer vision applications and are demanding on compute power. The computational workload of a convolution layer may involve deeply nested loops.

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Join ESD Alliance for Workshop on Mastering Digital-Driven Marketing and Sales

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By Bob Smith, EDA Cafe

It didn’t take much coaxing to convince OneSpin’s Nicolas Athanasopoulos and Dave Kelf from Breker to offer part two of their Digital Marketing Workshop series on best marketing practices for an effective social media strategy. They will be back Wednesday, October 3, with Digital Marketing Workshop 2.0, “Agility, Training and Collaboration ––The three key ingredients to master digital-driven marketing and sales.”

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Auto Chip Design, Test Changes Ahead

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By Kevin Fogarty, Semiconductor Engineering

The automotive industry’s unceasing demand for performance, coupled with larger and more complex processors, are driving broad changes in how electronics are designed, verified and tested.

What’s changing is that these systems, which include AI-oriented logic developed at the most advanced process nodes, need to last several times longer than traditional IT and consumer devices, and they need to work under conditions that even a year ago would have been considered unrealistic. This is forcing changes from one end of the supply chain to the other, raising questions about how this will impact time to market, cost, and which approaches ultimately will work best.

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Cracking The Auto IC Market

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By Ann Steffora-Mutschler, Semiconductor Engineering

The market for automotive electronics is booming, and it has set off a global scramble among established chipmakers and startups.

What’s becoming clear, though, is that not everyone understands just how different automotive is from the mobile market. Mobile is still the highest-volume market for semiconductors, but the growth has flattened. In contrast, the value of the automotive electronics market is rising quickly, and more chipmakers are attempting to stake a claim.

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Processing In Memory

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By Ed Sperling, Semiconductor Engineering

Adding processing directly into memory is getting a serious look, particularly for applications where the volume of data is so large that moving it back and forth between various memories and processors requires too much energy and time.

The idea of inserting processors into memory has cropped up intermittently over the past decade as a possible future direction, but it was dismissed as an expensive and untested alternative to device scaling. Now, as the benefits of scaling decrease due to thermal effects, various types of noise, and skyrocketing design and manufacturing costs, all options are on the table. This is particularly true for applications such as computer vision in cars, where LiDAR and camera sensors will generate streaming video, and for artificial intelligence/machine learning/deep learning, where large volumes of data need to be processed quickly.

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Using More Verification Cores

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By Brian Bailey, Semiconductor Engineering

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for Oski Technology; and Bill Mullen, senior director for R&D at ANSYS. What follows are excerpts of that conversation.

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