Others see the need for languages that span multiple levels of abstraction. Today, SystemC is heavily used for the development of blocks that process specific algorithms, says David Kelf, vice president of marketing for OneSpin Solutions. Transaction-level models of the algorithmic processing components in a chip are modeled using C, with a SystemC wrapper. These are verified and then synthesized into Verilog.
The escalating cost, time, and risk associated with custom integrated circuit (IC) fabrication has driven increased field programmable gate array (FPGA) usage across electronics applications. FPGAs are larger, faster, and more power-efficient than ever, and bring a number of capabilities unavailable in custom silicon design, such as field updates, multi-function devices, and simplified prototyping, making them an attractive option.
The ISO 26262 safety standard lays out a number of best practices for the automotive industry and for suppliers. Formal verification provides a way of streamlining the verification of SoCs that need to conform to the standard...
Peggy Aycinena inteviews Dave Kelf on OneSpin, Quantify Observation Coverage and DAC. OneSpin will demonstrate Quantify in Booth #1219, June 2nd to 4th, from 9 a.m. until 6 p.m. at Moscone Center in San Francisco.
Are you having problems verifying your ASIC, ASSP, and SoC designs? Are you planning on attending the Design Automation Conference (DAC) this year? If you answered "yes" to both of these questions, then one company that would be well worth your time to visit is OneSpin Solutions.