Challenges For New AI Processor Architectures
By Brian Bailey, Semiconductor Engineering
Getting an AI seat in the data center is attracting a lot of investment, but there are huge headwinds.
Investment money is flooding into the development of new AI processors for the data center, but the problems here are unique, the results are unpredictable, and the competition has deep pockets and very sticky products.
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“Verification of the floating-point hardware will be crucial to meet the performance and power requirements for these chips,” says Rob van Blommestein, head of marketing at OneSpin. “Verification of floating-point hardware designs has long been considered a significant challenge. FPUs combine the mathematical complexity of floating-point arithmetic with a wide range of special cases that require complex control paths. What’s needed is a formal verification solution that verifies that the result of arithmetic operations, as computed by the hardware floating-point unit (FPU), accurately matches the IEEE 754 standard specification.”
