Can Debug Be Tamed?
By Brian Bailey, Semiconductor Engineering
Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time.
In some cases, different technologies can help each other out. “One key factor in debug is the simulation test that triggered and detected a given design bug,” explains Sasa Stamenkovic, senior field application engineer at OneSpin Solutions. “The shorter and more focused the test, the faster and easier it is to diagnose and fix the error. When the test is generated by formal verification rather than by a simulation testbench, debug is easiest. Formal verification considers all possible stimuli to prove or violate the assertions against the design. If a violation is found, a formal tool displays the precise stimulus sequence, known as a counterexample, that triggered the bug. Many formal tools also can export the counter-example as a simulation test to enable debug in a familiar environment. Since formal verification determines exactly how the bug was triggered and which signals are relevant, the generated test is indeed shorter and more focused than tests from constrained-random test benches.”