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Debug Tops Verification Tasks

By Ann Steffora-Mutschler, Semiconductor Engineering

There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are being developed to deal with an explosion of data. Add to that new packaging approaches, more complex interactions between different blocks and power domains, and an increasing emphasis on reliability for automotive and industrial applications, and the increased emphasis on debug begins to make sense.


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“While simulation has made significant progress on all three fronts, constrained-random testbenches and portable stimulus test case generation do a far better job of exercising a design than hand-written test vectors,” said Sasa Stamenkovic, senior field application engineer at OneSpin Solutions. “This increases the chances of setting up the right scenario to trigger the bug. Both approaches generate self-checking tests, so these checks plus user-written assertions greatly increase the likelihood of detection. Waveform viewers and other debug aids have become somewhat cleverer about what they display and how they display it. However, simulation provides no guarantees, and so major challenges remain.”


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