Formal and Simulation Covered Together
By Bryon Moyer, EE Journal
How do you know when your IC design is done? When can you declare verification victory? These are the questions that coverage is supposed to help with. When your verification has covered the entire circuit, for lack of a more precise way of articulating it, then you’re done. (At least, with that part of the verification plan…)
Well, OneSpin (we’ve talked about their formal technology before) says that they have customers still struggling with coverage. Design verification product specialist Nicolae Tusinschi’s assessment is that, “Accellera’s UCIS 1.0 standard enables some forms of coverage interchange but there are no efforts to expand it and the working group is currently inactive.” They’ve announced a solution they’re calling PortableCoverage that, he says, “goes well beyond the scope of UCIS by focusing on formal coverage and results, including model-based mutation coverage and links back to the verification plan.” Let’s dig into this.
4 Coverage Cases
First, to be clear, OneSpin isn’t claiming to do everything that UCIS hasn’t done yet in the world of coverage. Staying within the realm that they control, they’re helping to improve formal coverage assessment and then to integrate coverage metrics between simulation and formal verification. They help both to view simulation and formal coverage together (via their Verification Coverage Integration, or VCI, app) and to refine the verification plan (via their Verification Planning Integration, or VPI, app).
Through their Quantify tool and Coverage Closure App (CCA), they create four coverage buckets:
- Elements that were covered and passed verification
- Elements that were covered and failed verification (i.e., need to fix some bugs)
- Uncovered elements – this indicates a need for better assertions
- Uncoverable elements – these are things that you can test until the cows come home, and you’ll never get a result, because it’s untestable.
To be clear, their coverage work focuses on formal coverage – how good are the assertions? The integration with simulation is not so much about what’s been covered by simulation vectors, but rather about letting the simulation tool know what might or might not be worth trying to test. In other words, those “uncoverable” tests can be updated into the verification plan so that no one wastes time trying to test the untestable.