Mitigating Risk Through Verification
By Ann Steffora Mutschler, Semiconductor Engineering
Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.
“In addition to the many other benefits of assertions and/or cover properties, these can be used to generate certain types of coverage models automatically,” said Nicolae Tusinschi, product specialist, design verification at OneSpin Solutions. “In simulation, assertions and cover properties that are triggered define a form of coverage that is already integrated with other metrics, such as code coverage and functional coverage. In formal verification, assertions and cover properties are triggered, and these results, if not a must, should be integrated into the coverage database and coverage viewer along with the simulation metrics.”