DVClub San Jose OneSpin Tutorial "Formal for Simulation Savvy Engineers"

Wednesday, October 12, 2016 from 11:30 AM to 1:50 PM

Dave and Buster's, 940 Great Mall Drive, Milpitas, CA 95035

Join us for lunch at DVClub San Jose on Oct 12th

Hear how Simulation Savvy Engineers can use Formal without SVA hassles

Join us for lunch at DVClub when it returns to Dave and Buster’s in Milpitas on Oct 12th. At this event OneSpin will unveil Operational Assertions, an easy to understand, simulation-centric assertion library that still uses standard SystemVerilog and can work with any fully-capable formal tool.

Formal can increase coverage in a simulation environment while eliminating hard-to-write test vectors to duplicate complex scenarios, or exhaustive stimulus for critical blocks. However, two barriers to this use model remain: tying formal into simulation so the coverage results can be compared and easily writing quick assertions with confidence they are testing the right things. Both of these problems can now be solved.

We will deliver a short, 45 min. presentation on Operational Assertions, a SystemVerilog assertion library that allows for timing diagram-like, transaction level assertions that are easy to understand and relate directly to a specification element. We will demonstrate:

·       How to easily verify key blocks and scenarios without the hassle of deep SVA

·       How quickly create complex test scenarios and track down tricky bugs

·       How to generate comparable UVM tests directly from OA,

·       How to tie formal and simulation coverage data together

 

Register

There is no fee and lunch is included.  Please sign up here.  Seating is limited.

 

Win a Drone

Enter our “Game of Drones” for a chance to win a drone to be awarded after the tutorial presentation.

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