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The Challenge Of RISC-V Compliance

By Brian Bailey, Semiconductor Engineering

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that claim to be RISC-V have implemented the specification correctly?


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Formal verification often has been seen as a better way to show that things are not broken. “Full compliance must ensure not only that the core does what it is supposed to do, but also that it does not do what it is not supposed to do,” says Sven Beyer, product manager for Design Verification at OneSpin Solutions. “This latter requirement, which requires the exhaustive analysis of formal verification, is essential to detect hardware Trojans and other trust and security vulnerabilities.”


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