close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

In the news

Respecting Reset

By Brian Bailey, Semiconductor Engineering

Reset is one of the most important signals in a design and yet perhaps one of the least respected. What can go wrong and how to correct it.

Resets are a necessary part of all synchronous designs because they allow them to be brought into a known state. However, such a simple process can lead to many problems within an SoC.

[...]

Ashish Darbari, director of product management for OneSpin Solutions, puts it into simple terms. “Many people do not even realize what can go wrong with reset. They have become more aware of Clock Domain Crossing (CDC) issues, but the interaction of clocks with resets makes the problem even more interesting. Lots of things can wrong from a circuit point of view.”

Read more

Whatever Happened To High-Level Synthesis? | Experts at the Table, Part 3

By Brian Bailey, Semiconductor Engineering

Targeting FPGA resources, OpenCL, tackling safety and security issues, addressing IoT needs.

A few years ago, High Level Synthesis (HLS) was probably the most talked about emerging technology that was to be the heart of a new Electronic System Level (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high-level design and verification at Mentor, a Siemens Business; Dave Kelf, vice president of marketing for OneSpin Solutions; and Dave Pursley, product manager for HLS at Cadence. What follows are excerpts from the conversation.

Read more

Introducing Doc Formal: The Journey So Far

Ashish Darbari, Director of Product Management on TechDesign Forum

Between nature and nurture, it is difficult to say what plays a more important role in life. I was fortunate to reap the benefits of both. I grew up in Allahabad and belong to the third generation of engineers and scientists in one of the well-known twenty-one royal families of India, the Darbari family. Our pedigree destined me for a life devoted to the sciences. However I had no inkling back then that my career path would lead me to Intel, ARM, Imagination, and today OneSpin Solutions. How did I go from being a kid in India to becoming a formal verification fanatic? The truth is, I had a long way to go—and so did formal.

Read more

Whatever Happened To High-Level Synthesis? | Experts at the Table, Part 2

By Brian Bailey, Semiconductor Engineering

Playing in an IP integration world, defining verification flows and compatibility with a virtual prototype.

A few years ago, High Level Synthesis (HLS) was probably the most talked about emerging technology that was to be the heart of a new Electronic System Level (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high level design and verification at Mentor, a Siemens Business; Dave Kelf, vice president of marketing for OneSpin Solutions; and Dave Pursley, product manager for HLS at Cadence. What follows are excerpts from the conversation.

Read more

Moore’s Law: Toward SW-Defined Hardware | Part 2

By Ed Sperling, Semiconductor Engineering

Heterogeneity and architectures become focus as scaling benefits shrink; IP availability may be problematic.

Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress.

[...]

As scaling continues to slow, the real challenge is continuing the economic benefits of Moore’s Law, and that’s where EDA companies see a big opportunity.

“Small architectural changes can make dramatic changes in performance and power consumption, and this is where tools like high-level synthesis can make a difference,” said Dave Kelf, vice president of marketing at OneSpin Solutions. “Tools like that shape the design cycle so you can spend more time getting better power and performance out of a design. You also can take a design that’s already done and iterate more quickly. You’re stuck with a schedule, but you can shrink the design cycle and verification, which gives you the equivalent of a node of improvement.”

That kind of gain can delay the need to move to the next node every two years. On the flip side, faster tooling and better training on those tools can make a dent in how much time, and therefore money, is spent on the design side.

Read more

Speeding Up Neural Networks

By Ed Sperling, Semiconductor Engineering

Neural networking is gaining traction as the best way of collecting and moving critical data from the physical world and processing it in the digital world. Now the question is how to speed up this whole process.

But it isn’t a straightforward engineering challenge. Neural networking itself is in a state of almost constant flux and development, which makes it a moving target. There are more than 20 different types of neural networks today, and some are more in favor one month than the next. In addition, there isn’t a clear answer for what is the best type of processor to use. The commonly accepted metrics—work done per unit of energy, per millisecond, and for the lowest possible cost—still apply, but they can be weighted differently at different times in the development cycle.

[...]

What’s different about neural networking is that these networks can be trained to be more efficient, a pattern that follows development of the human brain. An infant has more neurons than an adult—a process known as synaptic pruning—and a successfully designed neural network should be become more efficient or capable over time.

“Networks train image processing and language processing,” said Raik Brinkmann, CEO of OneSpin Solutions. “Deep neural networks consist of several layers of networks. There is a race on for this technology, using multi-dimensional constructs.”

Brinkmann noted that the big problem is still the volume of data. “You want to go from a von Neumann to a data flow architecture. But what is the right architecture?”

So far that isn’t clear, and it probably won’t be for some time. No matter how far scientists and engineers have come with neural networking, and its application to machine learning and artificial intelligence, there are many years of work ahead.

Read more

Design Complexity Drives New Automation

By Ann Steffora Mutschler, Semiconductor Engineering

It now takes an entire ecosystem to build a chip—and lots of expensive tools.

As design complexity grows, so does the need for every piece in the design flow—hardware, software, IP, as well as the ecosystem — to be tied together more closely.

[...]

Dave Kelf, vice president of marketing at OneSpin Solutions, agreed that one of the most dramatic changes in the development flow relates to verification techniques. “Simulation has given away to the three-legged stool of simulation, emulation and formal verification, each with its own attributes and issues. Tying these technologies into one common methodology is complex to say in the least. Common coverage methods provide a cornerstone for evaluating progress across the three solutions, and indeed the Accellera UCIS (Unified Coverage Interoperability Standard) Working Group jumped on this idea to extend coverage cross platforms and vendors.”

Read more

Whatever Happened To High-Level Synthesis? | Experts at the Table, Part 1

By Brian Bailey, Semiconductor Engineering

What progress has been made in High Level Synthesis and what can we expect in the near future?

A few years ago, High Level Synthesis (HLS) was probably the most talked about emerging technology. It was to be the heart of a new Electronic System Level (ESL) flow. Today, we hear much less about the progress being made in this area.

Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high level design and verification at Mentor, a Siemens Business; Dave Kelf, vice president of marketing for OneSpin Solutions; and Dave Pursley, product manager for HLS at Cadence. What follows are excerpts from the conversation.

Read more

Press Contact

Michelle Clancy
» send an e-mail
» +1 503-702-4732