Formal verification of IEEE 754 floating-point hardware
The FPU App verifies that the result of arithmetic operations, as computed by the hardware floating-point unit (FPU), accurately matches the IEEE 754 standard specification. All exception flags, invalid operation, division by zero, inexact result, underflow or tininess, and overflow, are also checked. All major operations are supported out of the box with the exclusion of division.
Flexibility and configurability are crucial in the solution to any complex verification challenge. The FPU App supports all four standard rounding modes: roundTowardZero, roundTiesToEven, roundTowardPositive, roundTowardNegative. Half, single or double precision formats can be selected at a flick of a switch. Less common precisions can be accommodated with limited additional effort. Users can also selectively disable checks, for example to ignore specific flags or entire operations not yet implemented in hardware. Should the hardware feature intended deviations from the IEEE 754 standard, a set of high-level functions enables an elegant customization of the checks that precisely match such deviations. Conversion functions between different floating-point formats as well as between signed integers and floating-point numbers are also provided.
OneSpin’s FPU App dramatically increases development speed and quality of IEEE 754 floating-point hardware. It is easy to setup and does not require formal expertise.
The FPU App is seamlessly integrated with the OneSpin 360 verification platform. Engineers can use all 360 DV advanced debug features. Additional dedicated debug capabilities are available, including a convenient high-level view of floating-point data types that considerably speed up the analysis and debug process. Complexity issues are mitigated through the automatic selection of OneSpin’s most appropriate, best-in-class proof engines and strategies.