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Processor Verification App

Quick and exhaustive verification of implementation and proof of compliance to instruction set architecture (ISA) with no hardware vulnerabilities

RISC-V is an open-source hardware instruction set architecture (ISA) widely supported by IP, EDA, and software suppliers. Providers of RISC-V IP cores face a high bar for verification and compliance to the published ISA. Meeting these challenges is essential to successfully compete with older, well established ISAs with many silicon implementations and design-ins.

Providers of RISC-V IP cores face a high bar for verification and compliance to the Instruction Set Architecture (ISA). Meeting these challenges is essential to compete with older, well-established ISAs with many silicon implementations and design-ins. In addition, core providers need to ensure that their designs meet the trust and security expectations of their customers, including the absence of hardware Trojans that could enable adversary attacks. One particular challenge stems from the openness of RISC-V for custom extensions. These custom extensions enable end users the unprecedented freedom to split their SoC between hardware and software to match their application’s needs with relative ease. However, these custom extensions also create considerable verification challenges as they should not only work as intended, but also they must not break any other functionality of the core.

As part of the OneSpin Processor Integrity Solution, the Processor Verification App is the industry’s first tool to address the needs of both core providers and core integrators. It leverages OneSpin advanced formal verification expertise for high- integrity processor applications to exhaustively verify the implementation with minimal set up and runtime. There is a tabular built-in formalization of the standard RISC-V ISA in the Processor Verification App. Custom extensions can be formalized in the same way. The App then automatically translates both the standard and custom ISA into a set of SystemVerilog Assertions (SVA) using the unique OneSpin Operational Assertion approach. Operational SVA enables high-level, non-overlapping assertions that define end-to-end transactions and requirements in a concise, elegant way. OneSpin formal engines detect any inconsistencies between an RTL core implementation and the ISA.

The application of OneSpin GapFreeVerification™ goes beyond proving equivalence between the RTL and the set of Operational SVA: it also verifies that the set of assertions is sufficient to cover the RISC-V core design and ensures that there is no unverified RTL code. Any extra functionality in the design, including hardware Trojans, is detected and reported as a violation of the ISA. This includes the systematic discovery of any hidden instructions or unintended side effects of instructions. This enables both core providers and customers to have the highest confidence in the RISC-V core implementations.

The OneSpin Processor Verification App ensures that an IP core implementation does everything it is supposed to do and does not do anything it is not supposed to do. System-on-chip (SoC) designers can license a RISC-V core confident that it complies with the ISA specification, while IP vendors can support their own ecosystems and ensure that partners also comply. Further, SoC designers can add custom features to the RISC-V ISA to support their specific applications.

The OneSpin solution ensures that nothing is broken as features are added and is flexible enough to verify custom instructions and registers.

 

Download the RISC-V white paper

Download the Processor Verification App datasheet


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the Processor Verification App is the industry’s first tool to address the needs of both core providers and core integrators. It leverages OneSpin’s advanced formal verification expertise for high-integrity processor applications.

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OneSpin’s Operational SVA enables formal verification enthusiasts to develop high-level, non-overlapping assertions that capture end-to-end transactions and requirements in a concise, elegant way.

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The OneSpin 360 Design Verification (DV) product line leverages the most advanced, high-performance formal technology as the basis for a range of verification solutions, from automated design analysis to advanced property checking.

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OneSpin’s Quantify measures the quality of a formal verification test bench. It provides precise, actionable information on what parts of the design-under-test (DUT) are verified, and it highlights RTL code that could still hide bugs.

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OneSpin’s Connectivity XL App is the industry’s first and only solution for the efficient specification and formal verification of huge numbers of deep connections in multi-billion-gate chips.

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OneSpin’s VCI App enables users to export structural coverage results produced by OneSpin’s QuantifyTM in different database formats with a single command.

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OneSpin 360 DV-Verify adds coverage-driven assertion-based verification (ABV) to the DVInspect platform.

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In a systematic verification flow, requirements tracking and coverage play an indispensable role. Generally, this starts from requirements specification, where individual requirements are broken down into features, implementations, verification goals, and metrics.

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Design verification has a lot in common with human hygiene practices. The goal of both activities is to remove all dirt, grime, and bugs through an active process of establishing good hygiene.

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Fault-tolerant hardware development is no longer a niche and presents new challenges. Many engineers face the daunting task of having to examine countless faulty variants of their design in order to integrate and verify multiple safety mechanisms within complex Systems-on-Chip (SoCs).

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Learn more about metric-driven verification with OneSpin!

portrait of Sven Beyer

Sven Beyer, Product Manager Design Verification

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