Specification Validation

Advanced system register specification validation

Modern System on Chips (SoCs) contain hundreds of registers, and it is these registers that allow software drivers running on the multiple processors to control and monitor the range of hardware IP. Although to the software engineers the registers appear as a convenient address map, in actuality they are often flip flops buried deep in the hardware logic. Marrying the address map with the hardware registers is a critical function and mismatches represent a common source of bugs.

Given the complexity of modern, hierarchical address maps, development teams have adopted a variety of methods to keep the information consistent. Common formats such as IP-XACT and Accellera’s Register Definition Language (RDL) are used to catalog the address map and drive hardware and software development.

Agnisys has developed and marketed a range of tools to synthesize register elements in the hardware and also verify that existing register sets are compliant, thereby validating the specification.

Formal verification provides a natural mechanism to perform register map validation. Agnisys has built the OneSpin 360 LaunchPad platform in to their ARV tool to allow the registers specified in the address map to be identified through the bus structures and hardware within the various SoC blocks. In addition, the tool checks that the registers operate correctly through bus accesses, and ensures that performance goals are met.