RISC-V Summit 2019 – Day 3 | Rob Oshana
On our third day of the RISC-V Summit 2019, we met Robert Oshana, VP Software Engineering and R&D at NXP Semiconductors, who told us a bit more about his plans on advancing the software strategy of the RISC-V Instruction Set Architecture (ISA).
Download our white paper "Assuring the Integrity of RISC-V Cores and SoCs" and learn more about the verification of RISC-V cores to ensure full IC integirty.
