Assuring the Integrity of RISC-V Cores and SoCs

The open RISC-V processor architecture is shaking up the intellectual property (IP) and system-on-chip (SoC) worlds. There is great interest and much industry activity underway. However, successful RISC-V core providers will have to verify all aspects of integrity for their designs: functional correctness, safety, security, and trust. SOC developers evaluating potential RISC-V need to check that their standards for design integrity are fully satisfied. They may wish to re-run the core-level verification steps and then perform additional tasks to ensure that the cores have been integrated properly. Verification of RISC-V designs is especially challenging because of optional features, implementation flexibility, and provisions for customer extensions.

This paper presents the OneSpin RISC-V Integrity Verification Solution and discussed how its components verify all four aspects of design integrity at both the processor core and full-chip levels. It concludes by detailing some issues found by the OneSpin Solution on RISC-V core and SoC designs available as open source.

The open RISC-V processor architecture is shaking up the intellectual property (IP) and system-on-chip (SoC) worlds. There is great interest and much industry activity underway. However, successful RISC-V core providers will have to verify all aspects of integrity for their designs: functional correctness, safety, security, and trust. SOC developers evaluating potential RISC-V need to check that their standards for design integrity are fully satisfied. They may wish to re-run the core-level verification steps and then perform additional tasks to ensure that the cores have been integrated properly. Verification of RISC-V designs is especially challenging because of optional features, implementation flexibility, and provisions for customer extensions.

This paper presents the OneSpin RISC-V Integrity Verification Solution and discussed how its components verify all four aspects of design integrity at both the processor core and full- chip levels. It concludes by detailing some issues found by the OneSpin Solution on RISC-V core and SoC designs available as open source.

Table of contents

1. Introduction
2. RISC-V Background
3. RISC-V Verification Challenges
4. Good Design Hygiene
5. Verifying Functional Correctness
6. Verifying Safety, Security, and Trust
7. SoC-Level Verification
8. Results on Open-Core Designs
9. Summary

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