close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

SystemC/C++ Design Verification

Easy bug detection and functional verification of SystemC/C++ code prior to High-Level Synthesis

High-Level Synthesis (HLS) (aka behavioral synthesis) transforms algorithmic and potentially untimed design models often written in SystemC and C++ to fully timed Register Transfer Level (RTL) design blocks. HLS tools are particularly popular as a method to rapidly generate design components with varying microarchitectures, while optimizing algorithm processing datapaths rapidly and effectively. This provides substantial benefits in terms of flexibility and time-to-market. Consequently, HLS is now in use at many large semiconductor and electronic systems companies. However, the verification options for SystemC and C++ designs have not kept pace with the synthesis technology.

OneSpin’s SystemC/C++ Design Verification solution provides a formal verification environment allowing for easy bug detection and functional verification of SystemC/C++ code prior to high-level synthesis.

The need for a new HLS Verification Methodology

Simulation-style verification of HLS code is largely performed by compiling and debugging the design representation, linked with the Accellera OSCI SystemC Class Library, in a similar fashion to software test. Due to the limited availability of SystemC tools, much of the verification task is performed on the resulting synthesized RTL code, introducing a level of indirection that makes correcting issues at the SystemC/C++ level complex and time consuming.


The primary verification requirement is to allow thorough verification of algorithmic code prior to synthesis, in order to ensure that the abstract algorithm implementation is tested and fully optimized against the original specification, as well as avoiding long debug cycles.

In addition, artifacts of the SystemC standard, for example the lack of an unknown, or X, state, potential race conditions between threads, etc., result in further ambiguity that must be eliminated before synthesis. Specific issues related to this abstract design level may be easily tackled with the right verification methods, improving final design quality.

SystemC/C++ Formal Verification

OneSpin’s unique SystemC/C++ Design Verification solution enables a broad range of formal verification techniques to be applied to SystemC and C++ components with varying levels of timing and code abstraction.

Hardware issues, such as the detection of uninitialized value propagation, or the effects of undefined operations (e.g. array out-of-bounds) may be effectively detected using OneSpin’s automated apps at the SystemC/C++ level. A SystemC-specific automated arithmetic overflow check has been added to 360 DV-Verify, which allows for the inspection of number precision across algorithmic datapaths.

Full assertion-based formal verification is also provided that allows comprehensive, temporal SystemVerilog assertions or C-asserts to be tested against SystemC/C++ design code. This provides a rich verification capability that makes use of a common assertion mechanism that can also be applied to post synthesized HDL code.


More information…


OneSpin 360 DV-Verify™ goes beyond that by providing a unified, coverage-driven assertion-based verification flow, and including a full verification app library, as well as means for easy design exploration, all in one tool.

»Learn more about 360 DV-Verify™…

OneSpin's Arithmetic Analysis App exhaustively examines algorithmic implementations for loss of precision, as well as redundant bits, considering all possible operations of the algorithm.

»Learn more about the Arithmetic Analysis App…

Simulation-style verification of SystemC high-level synthesis (HLS) code is largely performed by compiling and debugging the design representation linked with a SystemC class library, in a similar fashion to a software test.

»Download the flyer…

OneSpin 360 DV-Verify extends the DV- Inspect platform with coverage-driven Assertion-Based Verification (ABV). Many entry-level formal apps allow for assertion generation for specific problems without a need for deep formal knowledge.

»Download the data sheet…

High-Level Synthesis (HLS) transforms algorithmic and potentially untimed design models often written in SystemC and C++ to fully timed Register Transfer Level (RTL) design blocks.

»Download the data sheet…

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.

»Read the full article on Tech Design Forum…

Get in touch!

Learn more about SystemC/C++ Design Verification with OneSpin

portrait of Dominik Strasser

Dominik Strasser,
Vice President Engineering,
Product Manager High Level Design Verification

» Contact