close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

A Core Challenge

By Nicolae Tusinschi, OneSpin a Siemens Business

A common verification methodology available to both RISC-V core providers and SoC teams integrating these cores is required.

Modern processor designs present some of the toughest hardware verification challenges. Verification is particularly challenging for RISC-V processor core designs, with many providers and many variations of implementation.


Related Links