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An Effective Way to Verify RISC-V Cores (Swedish)

By Nicolae Tusinshci and Wei Wei Chen, OneSpin: A Siemens Business

Modern processor designs present us with some of the toughest challenges in hardware verification. This is especially true when it comes to RISC-V processor cores, where there are a number of variations and implementations from a myriad of different sources. The article by W. W. Chen, N. Tusinschi and T. L. Anderson, OneSpin Solutions, was presented at DVCon Europe 2020 and describes a verification methodology available to both RISC-V kernel vendors and SOC teams working to integrate these kernels. It deals with functional correctness including compliance, detection of security vulnerabilities and verification of the reliability that no malicious logic has been entered. Detailed examples of design bugs discovered in real RISC-V cores have been included.


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