Multicore Debug Evolves To The System-Level
By: Ann Steffora Mutschler
Complexity is making this process more difficult, but new and better approaches are being developed.
Still, formal has an important role to play. “Some big challenges with multicore designs involve performance analysis, and the memory subsystem and fabric,” said Nicolae Tusinschi, product specialist at OneSpin Solutions. “Debugging an SoC with a single core is complex enough, and things get exponentially more complex as the number of cores increases. During this type of analysis, it is highly inefficient to deal with design issues that could have been detected in earlier phases. This is one of the reasons using a low-quality open-source core might not be the best choice, even when building a demonstrator. RTL bugs could slow down the project or even mask performance issues. The first step is to have high-quality core and IP models and setup an automated flow to formally proof that IPs are wired-up correctly. In many cases, it is also beneficial to do a formal verification of the fabric and memory subsystem to rule out deadlock and livelock conditions that are often missed in simulation,” he added.
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The second principle is to discard the processor-centric view of debug. Most bugs these days are down to system-level interactions. You won’t spot them by performing multiple uni-processor debug sessions and hoping the system interactions will take care of themselves. It requires a system-level view. In addition, processors aren’t the only complex structures on today’s chips. The behavior of NoCs and on-chip buses, custom logic, memory controllers and so on can have a significant influence on system behavior — and if you can take steps to observe and analyze their operation, not just CPU code execution, you will not only spot more bugs, but it will also become dramatically easier to find the root cause and fix them.
