In the news

By Nicolae Tusinschi

Die Verifikation von RISC-V-Cores stellt für Core-Anbieter und SoC-Integratoren mit Blick auf die Sicherheit, Funktionaliät und Vertrauenswürdigkeit eine Herausforderung dar. Eine von beiden Seiten nutzbare Lösung eines Drittanbieters kann hier helfen.

By Brian Bailey, Semiconductor Engineering

Getting an AI seat in the data center is attracting a lot of investment, but there are huge headwinds.

By Rob van Blommestein

As the level of abstraction increases, so too must the level of verification.

By Brian Moyer, Semiconductor Engineering

Regulations and compliance are inconsistent and often inadequate, but adding better security boosts cost and impacts performance and power.

By Brian Bailey

Time spent in debug is unpredictable. It consumes a large portion of the development cycle and can disrupt schedules, but good practices can minimize it.

By Ann Steffora Mutschler

Tapping into multiple services, both inside and outside a car, requires a rethinking of everything from architectures to security.

By John Hallman, Product Manager, OneSpin Solutions

Utilizing digital twins to reduce the risk of updates to programmable hardware introducing new vulnerabilities.

By Vlada Kalinic, SystemC Verification, Product Manager, OneSpin Solutions

Although SystemC/C++ coding styles have been used for many years, specific models have recently emerged to drive common design flows across engineering teams. These include abstract algorithmic design code as input for high-level synthesis (HLS) tools, virtual platform models for early software test, configurable intellectual property (IP) blocks, and many more.

HLS, which transforms “mostly untimed” abstract SystemC/ C++ design representations to fully-timed register-transfer-level (RTL) design blocks, is in use at many large semiconductor and electronic systems companies. These tools are particularly popular as a method to rapidly generate design components with varying microarchitectures, whilst rapidly and effectively optimizing algorithm-processing data paths. Their use on control logic, as well as components with more detailed timing in general, is also becoming more widespread.