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In the news

Incremental System Verification (Experts at the Table, Part 2)

By Brian Bailey, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, OneSpin; and Jim Hogan, Board Director, OneSpin

How does a PSS model get verified and who will create that model? What happens when models extend beyond the specification?

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom Anderson, technical marketing consultant for OneSpin Solutions. What follows are excerpts of that conversation.

[...]

Anderson: This is certainly an example of the way in which verification will influence design. You are playing with a level of parameters that affect what the hardware does. This is another dimension of the general problem.

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Chiplet Momentum Builds, Despite Tradeoffs

By Brian Bailey, Semiconductor Engineering | Feat. Sven Beyer, Product Manager Design Verification, OneSpin

Pre-characterized tiles can move Moore’s Law forward, but it’s not as easy as it looks.

Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent ‘chiplet’ market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness.

[...]

"The chiplet also offers more opportunities for both security vulnerabilities and hidden hardware Trojans," cautions Sven Beyer, product manager for design verification at OneSpin Solutions. "Integrators will expect the vendor to verify these aspects of integrity. The SoC team may wish to re-run some aspects of standalone IP verification as part of screening vendors and evaluating chiplets."

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Formal Engines Learn from Experience

By Chris Edwards, Tech Design Forum | Feat. Dominik Strasser, VP Engineering, OneSpin

[...]

OneSpin’s work found that solver orchestration based on machine learning is effective. The company is armed with more than two decades worth of collected designs that extend as far back as the team’s original work at Siemens in the early 1990s.

Dominik Strasser, vice president of engineering at OneSpin, says with the machine-learning functions: “Users do not normally have to pick proof algorithms and we now have a system that has faster proofs for time-to-hold,” adding that time-to-fail has rarely been an issue.

[...]

As part of its ongoing work into applying AI to formal, a new project at OneSpin is aimed at helping with the debug process. “The tool finds out which part is the culprit. This is a very difficult problem to solve and a task for the future but we have some intermediate results. But don’t hold your breath,” Strasser says.

Another path OneSpin aims to pursue is using deep learning to analyse verification data. “Maybe then the runtime prediction will get better results,” Strasser hopes.

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ESD Alliance Elects 10-Member Governing Council

Three New Members Join Returning Members

The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, today welcomed its newly elected 10-member Governing Council who will serve a two-year term.

Returning Governing Council members are:

Dr. Aart de Geus, chairman and co-chief executive officer (co-CEO) of Synopsys, Inc.

Dean Drako, president and CEO at IC Manage

Dr. John Kibarian, president and CEO of PDF Solutions, Inc.

Dr. Walden C. Rhines, CEO Emeritus of Mentor, a Siemens business

Simon Segars, CEO at Arm

Lip-Bu Tan, CEO of Cadence Design Systems

New Governing Council members are Dr. Raik Brinkmann, president and CEO of OneSpin Solutions, Dr. Prakash Narain, president and CEO of Real Intent and David Dutton, CEO of Silvaco. Robert P. Smith, executive director of the ESD Alliance, is also a member of the council.

The Governing Council was elected by the ESD Alliance’s voting members during the voting period that ended May 3. The new chair will be elected at the first meeting of the Governing Council meeting Thursday, May 23.

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Verification Challenges for RISC-V Adoption

By Tom Anderson, Technical Marketing Consultant, OneSpin Solutions | Posted on GSA Forum

Just a few years ago, the idea of an open-specification processor architecture with open-source implementations available would have been dismissed by many. Modern processor designs are highly complex, with such advanced features as multi-stage pipelines, multi-level caches, out-of-order execution, branch prediction, and memory pre-fetching. Beyond the hardware design, a huge ecosystem is needed. Reference design kits and software development platforms are essential. Operating systems and applications must be ported to the new architecture. A significant portion of the system-on-chip (SoC) industry must design-in the new processor and validate it in silicon. These challenges have appeared daunting indeed.

However, the introduction of the RISC-V architecture has defied conventional wisdom and is starting to disrupt the processor world. The original design was developed in the EECS Department at the University of California, Berkeley. The instruction set architecture (ISA), the primary processor specification, is now supported by the RISC-V Foundation. Its more than 200 members span semiconductors, systems, intellectual property (IP), software, academia, and more. Clearly there is a great deal of interest in this topic, but the industry has moved well beyond just curiosity. Many RISC-V cores, and even some SoCs built around these cores, are available as open source. Commercial cores also exist, and chips containing RISC-V processors are shipping. Many software titles have already been ported.

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The Case for Embedded FPGAs Strengthens and Widens

By Brian Bailey, Semiconductor Engineering | Feat. Tobias Welp, Engineering Manager, OneSpin

Combining the flexibility of a FPGA with the performance and cost benefits of an SoC is pushing this technology well into the mainstream.

The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs.

Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they need to launch products they know will need frequent updating.

Field programmable gate arrays (FPGAs) traditionally were considered too expensive for most applications and often relegated to prototypes or providing a time-to-market advantage for emerging standards. But the economics are changing. Integrating a reprogrammable fabric into an SoC is increasingly seen as a viable and valuable option.

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Machine learning is adding some new requirements into products. “FPGA fabric may be added to SoCs to enable variations in the engines and processors with domain-specific instruction sets,” points out OneSpin’s Welp. “In some cases, it may be possible to map algorithms for machine learning and other key applications into hardware and later refine the design as the results improve.”

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When Verification Leads (Experts at the Table, Part 1)

By Brian Bailey, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, and Jim Hogan, Board Director, OneSpin

Would an executable requirements document transform verification or design? Experts have differing ideas.

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, CEO for VTool; Adnan Hamid, CEO for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom Anderson, technical marketing consultant for OneSpin Solutions. What follows are excerpts of that conversation.

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Hardware Trojans and the Problem of Trust in Integrated Circuits

By Sergio Marchese, Technical Marketing Manager, OneSpin | Semiconductor Engineering Blog

IC development steps are vulnerable to malicious insertions that may compromise system security.

Electronic systems are at the core of an ever-increasing number of products and services. From power plants to automobiles, from medical devices to airplanes, from smartphones to home appliances, complex electronic systems enable an unprecedented level of automation, performance, safety, and security. Integrated circuits (ICs) are the backbone of these systems. It is of paramount importance that they can be trusted to operate in full compliance to their specifications and certifications. However, IC design, production, and distribution are surprisingly vulnerable to malicious agents that could infiltrate devices with poor performance and reliability, or even with hardware Trojans, i.e., additional, hidden functionalities designed for nefarious purposes.

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