close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

In the news

RISC-V: More Than A Core

By Brian Bailey, Semiconductor Engineering

The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V’s success.

[...]

The EDA industry is beginning to respond, too. “I expect that the RISC-V ecosystem will extend beyond IP,” says Tom Anderson, technical marketing consultant for OneSpin Solutions. “The numerous implementations offer opportunities and users for EDA vendors. This is a brand-new ISA, so there is already considerable interest in formally verifying implementations against the ISA. I expect EDA vendors to offer verification IP (VIP) and formal apps to help their users verify their RISC-V designs.”

Read more

ESD Alliance Workshop on Digital Marketing: Tools and Sales

By Paul McLellan, Cadence Breakfast Bytes Blogs

Yesterday was the first part about the ESD Alliance Digital Marketing workshop. Today, it is part 2 (of 2).

Today's marketers need to be hands-on since there are a lot of different aspects and it is too slow (not agile) to have to use different organizations for everything. Getting from here to there requires training, and there is a lot around. I'm going to skip over a lot of what Nicolas said and jump to his recommendations. Note that these recommendations are for small and medium-sized companies. In a big company, there will almost certainly be a CRM system like Salesforce already in place, and perhaps other tools too.

He had a lot more recommendations than these, too many for a blog post like this. I try my best, but a post like this is no substitute for being at the workshop yourself. You should have been there.

Read more

11 Myths About Formal Verification

By Tom Anderson, Electronic Design

Formal verification is used by almost every chip development and verification group, though myths about it persist and may deter engineers who could benefit from its value.

Read more

ESD Alliance Workshop on Digital Marketing: Agility

By Paul McLellan, Cadence Breakfast Bytes Blogs

Last week the ESD Alliance ran another workshop on digital marketing, with Nicolas Athanasopoulos of OneSpin and Dave Kelf (now at Breker, but who used to work with Nicolas at OneSpin).

Nicolas had two main messages:

- Digital marketing requires agility: start small, analyze, optimize, and repeat.

- Training is key: there are a lot of digital marketing tools.

Read more

Experts at the Table, Part 2: So Many Waivers Hiding Issues

By Brian Bailey, Semiconductor Engineering

Domain crossings can produce thousands of waivers. How does a team put in place a methodology for dealing with them?

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications engineering, scientist for Synopsys. What follows are excerpts of that discussion.

Read more

Adding Safety Into Automotive Design

By Ann Steffora Mutschler, Semiconductor Engineering

OEMs are demanding safety-readiness for more components, altering the dynamics of the design process.

[...]

Also, ISO 26262 compliance requires robust computation of several hardware metrics, including single-point fault metric (SPFM), latent fault metric (LFM), and the probabilistic metric for random hardware failures (PMHF), noted Jörg Grosse, product manager functional safety at OneSpin.

[...]

“Typically this is done within the FMEDA, which is owned by the functional safety engineers. We are observing confusion and increasing effort when it comes to computing those metrics for SoCs because tasks are pushed across to the functional verification teams without clear methods or tool flows. Massively increased chip size, shrinking geometries, and higher frequencies are imposing new challenges for compliance, such as new classes of failure modes. Innovation and re-assessment of current flows and methods are needed to ensure that crucial resources are effectively used and to prepare for these new challenges,” he said.

Read more

RISC-V Inches Toward The Center

Semiconductor Engineering logo

By Ann Steffora-Mutschler, Semiconductor Engineering

RISC-V is pushing further into the mainstream, showing up across a wide swath of designs and garnering support from a long and still-growing list of chipmakers, tools vendors, universities and foundries. In most cases it is being used as a complementary processor than a replacement for something else, but that could change in the future.

[…]

Read more

Domain Crossing Nightmares I Part 1

Semiconductor Engineering logo

By Brian Bailey, Semiconductor Engineering

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications engineering, scientist for Synopsys. What follows are excerpts of that discussion.

[…]

Read more

Press Contact

portrait of Nanette Collins

Nanette Collins
» nanette@nvc.com
» +1 617 437 1822