OneSpin sees two trends dominating the semiconductor and EDA industry for 2019. The first is that security and trust will start becoming key requirements for many applications. Prevention of hardware vulnerabilities and protection from attacks are essential to ensure safety, data privacy and availability of essential infrastructure. Today, this field is dominated by software, but it has become clear that hardware must play a bigger role in addressing this challenge. Similar to safety, where standards such as ISO 26262 and hardware safety mechanisms protect systems against systematic and random failures, we will see the emergence of security standards. They will prescribe strict hardware development processes in order to avoid vulnerabilities and hardware security mechanisms that protect electronic systems from adversary attacks.
As the cost of chip turns has grown from thousands to millions of dollars, missed design bugs are unacceptable.
Chip design verification used to be straightforward, if not always easy. Verification engineers (sometimes designers playing a double role) created a spreadsheet of all of the design features and then wrote a test to verify each one. As tests were written and passed in simulation, the features were checked off on the spreadsheet, which served as a de facto verification plan. When all of the tests were passing, verification was declared complete, and the chip was released to place-and-route and — eventually — taped out.
Three changes rendered this relatively simple approach inadequate. First, incredible growth in size and complexity of digital designs meant that it was hard to think of all of the features and all of the tests needed to verify them. This was especially true for corner-case conditions, often involving combinations of features in specific configurations. Verification engineers cited their mantra, “If it isn’t tested, it’s broken,” and worried that they were missing key functionality. As the cost of chip turns grew from thousands to millions of dollars, missed design bugs became unacceptable.
By Ann Steffora Mutschler, Semiconductor Engineering
Agile development is gaining traction for developing hardware testbenches, but challenges remain.
Sergio Marchese, technical marketing manager at OneSpin Solutions, noted that his company has adopted many Agile techniques for R&D. “On the hardware side, while there is some consensus that Agile can reduce development waste and foster a more co-operative working environment, there has been limited adoption. One of the exceptions is verification and, in particular, formal verification.”
As a verification engineer, he had a number of successful experiences applying Agile principles. “A key benefit of Agile hardware development is that the turnaround time to identify and fix a bug, and verify the new RTL version, can be reduced dramatically, from days to minutes in complex projects,” he said. (See Fig. 1.)
Formal verification tools enable this type of process. “Designers can use formal tools themselves to execute automated checks and quickly explore intricate design functions without the need of a simulation testbench,” Marchese said. “They also can work side-by-side with verification engineers to develop end-to-end assertions in a form of pair programming aimed at delivering correct code iterations. The ultimate measure of success is that traditional, non-Agile verification should then find few or no bugs at all.”
Still, this isn’t always so easy.
“While the hardware community has an increasing interest in Agile methodologies, fueled by its success in software projects, it is clear that Agile methodologies cannot be applied to hardware projects without some adaptation,” said Marchese. “Furthermore, companies aiming to fully embrace Agile need to change their engineering culture, which is a gradual and complex process.”
The holiday season is all about traditions, and the annual holiday puzzle has become a tradition here at OneSpin. Two years ago, we challenged engineers everywhere to solve the famous Einstein’s Riddle using a formal tool. We received some interesting solutions. Last year, we drew an even bigger response to our invitation to tackle the “World’s Hardest Sudoku.” These puzzles are fun, of course, but the different approaches taken by those submitting solutions also reveal a lot about the power and flexibility of assertions and formal verification.
Artificial Intelligence (AI) has inspired the general populace, but its rapid rise over the past few years has given many people pause. From realistic concerns about robots taking over jobs to sci-fi scares about robots more intelligent than humans building ever smarter robots themselves, AI inspires plenty of angst.
By Ann Steffora-Mutschler, Semiconductor Engineering
There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are being developed to deal with an explosion of data. Add to that new packaging approaches, more complex interactions between different blocks and power domains, and an increasing emphasis on reliability for automotive and industrial applications, and the increased emphasis on debug begins to make sense.
By Ann Steffora-Mutschler, Semiconductor Engineering
Optimizing designs for power is becoming the top design challenge in battery-driven IoT devices, boxed in by a combination of requirements such as low cost, minimum performance and functionality, as well as the need for at least some of the circuits to be always on.