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Prototypes Proliferate

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By Brian Bailey, Semiconductor Engineering

Custom hardware also provides other benefits. “Emulators, particularly those based on custom chips, have a number of advantages,” says Dave Kelf, vice president of marketing for OneSpin Solutions. “They tend to offer faster compile times and therefore a tighter debug turnaround loop, they have greater visibility into the design, and have better connections with simulation and the EDA flow.”

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Verifying AI, Machine Learning

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By Dr. Raik Brinkmann, Semiconductor Engineering

Raik Brinkmann, president and CEO of OneSpin Solutions, sat down to talk about artificial intelligence, machine learning, and neuromorphic chips. What follows are excerpts of that conversation.

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System Coverage Undefined

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By Dr. Ashish Darbari, Semiconductor Engineering

When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it’s the one verification engineers lose sleep over.

Exhaustive coverage has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block have been verified. But those metrics and methodologies have struggled to keep up with growing complexity, and they do not scale to the system level. A new framework for understanding coverage and completeness is required.

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DVCon Europe Takes Over Munich October 16-17

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By McKenzie Ross, Semiconductor Engineering

DVCon Europe is on the horizon, and this year’s program should prove to be very timely. Chips and systems are getting more complex, verification is becoming more difficult, and formal has emerged as a critical piece of the verification suite

The lineup this year tackles some key issues facing a changing semiconductor landscape. During a Monday tutorial, “Next Generation ISO 26262-based Design Reliability Flows,” Jörg Grosse, product manager functional safety, and Sanjay Pillay, Austemper Design Systems’ CEO, will demonstrate a complete safety development process.

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Behind the Curtain at the DVCon Europe Exhibition

By Dave Kelf, DVCon Europe Blog

DVCon Europe is known as a source of practical insight into electronic design techniques and methods. Past attendees are aware that the unusually large number of tutorials for a conference of this size, together with a range of interesting papers, as well as keynotes and panels, offer all kinds of valuable information that can improve their skills and knowledge. What is less apparent is the technical wealth of data provided in the exhibition.

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Doc Formal: The evolution of formal verification – Part Two

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By Dr. Ashish Darbari, Tech Design Forum

This is the second part of an analysis as to how formal verification has evolved so that it can now be applied to major project challenges. Having described the technology’s foundations in Part One, this article moves on to look at real-world contemporary uses of formal as illustrated by practical examples.

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When Is Verification Complete?

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By Ann Steffora Mutschler, Semiconductor Engineering

This isn’t always possible, and not everyone agrees this is necessary. “You don’t have to wait until you get the plan because you will never get the plan because you will never get the specs,” said Ashish Darbari, director of product management at OneSpin Solutions. “The designers’ work is to write some code. ‘I am a directed test person. Ashish came along and told me to write assertions. I love my assertions. Here is an assertion, run coverage. I’m actually covering 30% of this design with this assertion. Okay, another one discovers now I’m at 50%. Oh no, I actually now have a bug because this check I added exposed a bug in my design and now my coverage has gone down.’ Coverage needs to begin the first hour of the design window. If you don’t do that it won’t help.”

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