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In the news


Do Parallel Tools Make Sense?

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By Brian Bailey, Semiconductor Engineering

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for Oski Technology; and Bill Mullen, senior director for R&D at ANSYS. What follows are excerpts of that conversation.

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Auto Chip Test Getting Harder

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By Kevin Fogarty, Semiconductor Engineering

Chipmakers and test/validation companies are helping lead the effort to develop self-driving cars, but they are facing a wide range of technical and even cultural barriers.

Advanced driver assist systems (ADAS) already are the most complex systems by far in modern cars, the best of which hover between Level 2 and Level 3 on the five-step autonomy ladder maintained by the Society of Automotive Engineers (SAE) since 2016. To get to Level 3 and eventually Level 4 will require deep-learning and real-time decision-making, incorporating data from LiDAR, sonar, radar, vision systems, navigation, vehicle recognition and pedestrian recognition.

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Virtual Verification Smorgasbord

By Amelia Dalton, EE Journal

Are you ready for a virtual buffet of verification goodness? I hope so. In this week’s Fish Fry, we’re gobbling down as much verification as we possibly can fit on our podcastin’ plate. First up, Anupam Bakshi (Agnisys) joins us to dish on register specification, automatic memory verification, and UVM model integration. Next, Dave Kelf (Breker) serves up some delectable details about their new Trek Five product, the history of portable stimulus, and how Breker has been integral to the portable stimulus group at Accellera. To finish things up, Vladislav Palfy joins us to discuss the biggest trends in the world of formal verification.

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More Sigmas In Auto Chips

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Ann Steffora-Mutschler, Semiconductor Engineering

The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems.

This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these devices, because they have to be designed in the context of other systems. Some of those systems are still deep in the development phase.

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Why Parallelization Is So Hard

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By Brain Bailey, Semiconductor Engineering

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for Oski Technology; and Bill Mullen, senior director for R&D at ANSYS. What follows are excerpts of that conversation.

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Pros, Cons Of ML-Specific Chips

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By Brain Bailey, Semiconductor Engineering

Machine Learning’s Limits, part 3: Which processor type is the best for training and inferencing, and why are there so many companies trying to build new processors specifically for machine learning and AI?

Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation.

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Functional Safety: Art Or Science?

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By Sergio Marchese, Semiconductor Engineering

Nowadays, most hardware development projects deploy functional verification flows that include UVM-based constrained-random testbenches and formal verification. High design complexity, tough budget constraints, and short time to market are the norm, not the exception. Advanced verification is a necessity for many engineering teams. In our increasingly connected world, where billions of IoT devices soon will be communicating to us and to each other, security rapidly is becoming a key concern.

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