By Ann Steffora Mutschler, Semiconductor Engineering
Methodologies for integration become a competitive tool as complexity and possible options skyrocket.
As chip complexity increases, so does the complexity of IP blocks being developed for those designs. That is making it much more difficult to re-use IP from one design to the next, or even to integrate new IP into an SoC.
What is changing is the perception that standard IP works the same in every design. Moreover, well-developed methodologies for reuse can give a chipmaker a competitive advantage. The final shape of the design depends on various factors, such as application demand, and interfacing or power requirements, all of which increase the number of possible configurations.
And that’s not easy because once the IP is changed from one product to another, the register map goes out the window. In order to maintain the register map, the IP must be managed intelligently.
Dave Kelf, vice president of marketing at OneSpin, said that in some cases, management is happening in much the same way that software engineers manage software blocks using a repository with version control and multitasking. “With globalization, more engineers are getting at the IP within an organization, so the repository has to be available for more than one team working on an IP block. That’s a big issue.”
As far as how IP reuse evolves, time will tell but given things like safety and security being built in where it wasn’t before, along with IP blocks getting bigger and bigger calling into question the very definition of an IP block, one can imagine a hierarchy of IP, he said.
Rising complexity, diverging market needs and time-to-market pressures are forcing companies to rethink how they deal with defects.
“Die size is increasing while feature structure size and voltage levels are decreasing,” said Raik Brinkmann, CEO of OneSpin Solutions. “So you need less energy to create an issue. That requires more error correction and TM (triple modular) redundancy. But it also makes it harder for design and verification.”
Brinkmann noted that the situation is somewhat relieved by machine learning because noise is part of the algorithm and robustness is built in, so certain type of faults would be just noise and cause no harm.
By Ann Steffora Mutschier, Semiconductor Engineering
Designing chips for the automotive market is adding significant overhead, particularly for chips with stringent safety requirements.
On the verification side it could result in an additional 6 to 12 months of work. On the design side, developing the same processor in the mobile market would take 6 fewer man months. And when it comes to complex electronic control units (ECUs) or SoCs, the difference is more dramatic.
Functional verification was already tough enough, but having to identify behaviors that were never defined or intended opens up the search space beyond what existing tools are capable of handling.
However, while you may not be able to eliminate unintended behaviors, a design team is not helpless. There are several steps that can be taken to reduce the likelihood of these problems getting into the design. And even if they make it into the design, there ways in which these issues can be handled so that extreme situations are avoided. (Part one of this series explored some of the ways in which unintended behaviors can find their way into both the hardware and software and some of the ways in which they can be detected.)
DVCon generates a lot of respect, and for good reason. Engineers have attended this conference for over 25 years to further refine their skills in the area of design and verification. Yet, there’s a problem in paradise.
In an industry like EDA that’s super dominated by just three players, there’s little if any room in the industry – or at a conference like DVCon – to showcase the ideas and innovations of the Small Guys. The Big Guys teach tutorials and present papers; the Small Guys get to hang posters in the hallways.
All of that was supposed to change tonight thanks to the sponsorship of the ESD Alliance and OneSpin Solutions, as well as Vista Ventures’ Jim Hogan.
Tonight, six of the Small Guys in verification appeared on a panel moderated by Hogan hoping to get their 60-minute shot at fame. A post-Happy-Hour hour in which to lay out their case for customers to come and sample the kind of innovation that everyone knows is the watchword of technology startups, particularly in EDA.
Depending upon your point of reference, artificial intelligence will be the next big thing or it will play a major role in all of the next big things.
This explains the frenzy of activity in this sector over the past 18 months. Big companies are paying billions of dollars to acquire startup companies, and even more for R&D. In addition, governments around the globe are pouring additional billions into universities and research houses. A global race is underway to create the best architectures and systems to handle the huge volumes of data that need to be processed to make AI work.
OneSpin's Dr. Ashish Darbari sat down with Sanjay Gangal of EDACafe at DVCon '17 to provide a 5 minute update on the state of Formal technology, use models, latest developments and his new position at OneSpin.