Formal verification can be used for many things, but one is to ensure that synthesis performs correctly and that the behavior of the output netlist is the same as the behavior of the input RTL. OneSpin EC equivalence checking ensures that the RTL design and the output gate-level netlist will produce the same results for the same inputs under all circumstances.
OneSpin Solutions and Oasys Design Systems have signed an original equipment manufacturer (OEM) agreement. OneSpin 360 EC-ASIC is being used for synthesis verification, comparing two representations of the same design before and after synthesis to ensure functional equivalence.
A few weeks ago, I asked many people in the industry for their predictions for 2013. I separately asked for those related to technology in general, to the EDA industry and for business predictions. In this first part I will be presenting their technology predictions.
It seems as if 2012 was a good year for almost all of the respondents of my 2012 survey and many of them have some good news to share. OneSpin Solutions took a lower profile mid-year 2012 and was rewarded with the opportunity to reassess the verification space.
Bis um den Faktor 10 bescheunigt das automatische Werkzeug RootCauseAnalyzer von OneSpin die Fehleranalyse in Assertions und Designs. Der Entwickler hat damit ein Hilfsmittel, um die Ursache zu finden, warum eine Zusicherung bei der funktionalen Verifikation eines RTL-Designs fehlgeschlagen ist.