In the news

By Ashish Darbari, Tech Design Forum

Who would have thought the New Year would start on such a rocky note for all things digital? I am talking, of course, about Spectre and Meltdown.

I admit I didn’t pick up the signs when trouble started brewing last June. Having done some research, the problems appear to have been kept deliberately under wraps, so that hackers would not immediately start looking for exploits.

Sergio Marchese, Semiconductor Engineering

Automated apps have driven widespread adoption of formal, so now more engineers seek to become experts.

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Who doesn’t like a great family picture during the festive season? Of course, those occasions call for reasonably elegant attire. When in the spotlight, most people like to get somewhat more formal.

It seems that in the semiconductor world, it’s the reverse. As formal verification transitioned from a niche technology to mainstream over the past few years, formal verification engineers and their work have enjoyed increased attention at conferences and trade shows. Panels, paper presentations, and even entire events dedicated to the latest applications of formal verification are more prevalent than ever.

This trend is set to continue. With complex electronics extending its reach well beyond computers, smartphones, and networks to become a key differentiator in cars, wearables, and even thermostats, the need for solutions enabling secure, safe, and right-first-time hardware can only increase.

Cloud-based verification and software development, bigger IP blocks, machine learning, and security issues top the list for 2018.

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It also may bring new classes of tools into existence. “Building reliable and accountable machine learning models will have a direct impact on design practices and development tools because machine learning is essentially a statistical method,” says Raik Brinkmann, president and CEO of OneSpin Solutions. “This is very different from the traditional engineering practices. New types of bugs, such as data-driven ones, need to be addressed.”

As data rather than people define the specification, validation of data with regard to its ability to cover all relevant application scenarios becomes a new challenge, Brinkman says. “A combination of traditional methods, such as requirement engineering or formal analysis with statistical, data-driven approaches will be required. As a result, new tools will be needed to support these processes.”

By Brian Bailey, Semiconductor Engineering

Part 1 of 2: How do you trade off cost and safety within an automobile? Plus, a look at some of the challenges the chip industry is facing.

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But you also have to prove that those safety mechanisms are up to the task. “Hardware safety mechanisms are a core ingredient to enable functional safety and they need to be verified from both qualitative and quantitative perspectives,” says Jörg Grosse, product manager for functional safety at OneSpin Solutions. “Since the purpose of hardware safety mechanisms is to protect against random faults, some type of fault injection is recommended by the safety standards to verify them. On a basic level, this means that a tool must inject a fault and verify that the safety mechanism can detect it.”

New architectures, materials and equipment could have a huge impact on the chip industry.

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This could lead to different types of partnerships. “As the vertical integration between engineering methods and tools progresses, and systems companies or OEMs need to become more silicon driven, a deeper integration of EDA tools with systems engineering tools will be required,” says Raik Brinkmann, president and CEO of OneSpin Solutions. “This may also have an impact on alliances and M&A activity.”

By Brian Bailey, Semiconductor Engineering

What remains to be done before liquid IP becomes a standard practice? What issues are preventing adoption today?

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This is interesting because it concerns me. If we don’t see everything moving up and see stuff remaining at RTL, then it is just connecting things. But it is creating a barrier to everything moving up, and if you get into the holy grail of synthesizable model also being used in virtual prototyping, then that would be phenomenal. But it sounds as if we are no longer pushing toward that.

By Ann Steffora Mutschler

“Operational scenarios that would normally be deemed either not possible or not sensible by hardware designers and architects, and thus likely to be overlooked, suddenly become relevant. Both hardware failures and malicious attacks may drive the chip and the car into forbidden territory. Formal verification enhanced with fault injection systematically uncovers all these hard-to-foresee scenarios,” said Sergio Marchese, technical marketing manager at OneSpin Solutions.

by Brian Bailey, Semiconductor Engineering

Second of two parts: Progress on 2017 predictions was slow and steady, apart from one big miss in the standards area.

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Coverage is a connection point between several aspects of a verification flow. “The emerging Portable Stimulus standard has a notion of scenario coverage that applies to all the tools to which it ports,” points out David Kelf, vice president of marketing for OneSpin Solutions. “This helps provide a common coverage model that provides the right level of feedback on the verification of design requirements, not just code testing.”