Chip Design Verification Community’s Travel to San Jose for DVCon
By Bob Smith, EDA Cafe
DVCon is a yearly gathering of the chip design verification community held at the DoubleTree Hotel in San Jose. I’m certain its organizers and steering committee are pleased with attendance, the program, the exhibit floor and the opportunity for attendees to network. The mood was serious and intent on learning –– after all, chip design verification is a huge and complex problem. Nonetheless, everyone was in great spirits.
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OneSpin’s Product Manager Sven Beyer (left) and Sasa Stamenkovic, senior FAE, are ready to talk about its recent announcement –– completion of a series of factory inspections and audits of its organization and tool development by internationally recognized testing body TÜV SÜD. The first Tool Qualification Kit is available for OneSpin 360 EC-FPGA, an automatic sequential equivalence checker for FPGA design.
