DVCon USA 2019 preview: OneSpin
OneSpin will formally unveil its formal RISC-V Integrity Verification Solution for development and assessment of the open-source IP at DVCon next week (Doubletree Hotel, San Jose, February 25-28). The company is exhibiting at Booth #301. The product will also be on view at EmbeddedWorld in Nuremberg on eVision System's booth (Hall 4, Booth 4-560).
OneSpin sees the verification of an instruction set architecture’s (ISA's) conformance as a natural fit for its formal verification technology. The RISC-V Integrity Verification Solution is based on the RISC-V ISA formalized in a set of SystemVerilog Assertions, delivered as a series of formal apps, and integrated into a verification framework. It thus verifies compliance with the open standard RISC-V ISA.
OneSpin says that the product has been validated using leading RISC-V core implementations. The platform undertakes an extensive formal analysis of implementations and features a bug-hunting environment to quickly uncover corner-case bugs.
OneSpin says that the formal bug-absence core assessment environment checks for unbounded proofs and includes systematic discovery of all hidden instructions or unintended side effects of instructions. Detection of hardware Trojans for trust assurance and detection of security vulnerabilities is also included
