How To Integrate An Embedded FPGA
By Brian Bailey, Semiconductor Engineering | Feat. Tobias Welp, Engineering Manager, OneSpin
Adding an eFPGA into an SoC is more complex than just adding an accelerator.
Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric itself?
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Formal verification can help. “The FPGA fabric must be verified twice, first by the vendor and then by the user programming it,” explains Tobias Welp, engineering manager for OneSpin Solutions. “Formal equivalence checking, a key verification step, is even more important when fabric is involved because FPGA synthesis tools offer advanced optimizations to meet power, performance, and area (PPA) goals. Some of these optimizations change the state space of the design and move logic across register boundaries, so sequential equivalence checking is required. This should be performed in multiple stages to ensure that the input RTL, the post-synthesis netlist, the placed-and-routed netlist, and the programming bitstream are all functionally equivalent.”
