Why Your FPGA Synthesis Flow Requires Verification
By Tom Anderson, Semiconductor Engineering
Equivalence checking was key to making logic synthesis mainstream, but it’s more complex when it comes to FPGAs.
[…]
When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requirements for speed, area and power. These same requirements must continue to be satisfied after the full place-and-route process is complete. Modern synthesis tools are complex with both advanced algorithms and many “knobs” for user guidance.
