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OneSpin Solutions unveiled a formal RISC-V Verification App. The App is intended to exhaustively verify that RSIC-V cores are developed and integrated with zero bug escapes and guarantee full compliance with the ISA, even with the range of configuration options available. OneSpin says the automated solution needs only a few days to set up and only two hours to run on a complete core. In addition, OneSpin’s 360 EC-FPGA now supports three Intel FPGA families, Stratix 10, Arria 10, and Cyclone V using Intel Quartus software for synthesis and place-and-route. The company says the move to support FPGAs used in high-bandwidth applications meets demand from verification engineers for formal equivalence checking solutions that ensure functional correctness of FPGA designs. The tool is implemented in the FPGA flow from RTL to place-and-route to check RTL code against a post-synthesis, gate-level netlist.
OneSpin Solutions has extended its EC-FPGA automated sequential equivalence checking software to cover three of Intel’s field programmable gate array (FPGA) lines: Stratix 10, Arria 10 and Cyclone V.
The company has also launched an app for use inside its RISC-V Integrity Verification Solution aimed at safety- and security-critical applications and specifically targeting the increasingly popular open-source core.
By Brian Bailey, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, and Jim Hogan, Board Director, OneSpin
The role of a verification engineer will change and start to look a lot like knowledge management.
Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom Anderson, technical marketing consultant for OneSpin Solutions. What follows are excerpts of that conversation.
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Anderson: We are dancing around the idea of correct by construction. It has been around forever. Would you want a model that you don’t have to verify? That is the goal of correct by construction. You have a model that is correct, maybe through exploration, maybe through other techniques that you used to validate and verify what you are worried about. But it is a single model, and from that you generate the design. Maybe we are getting to the point where the top level of an SoC, defined to be correct by construction, may actually work.
By Brian Bailey, Semiconductor Engineering | Feat. Tom Anderson, Technical Marketing Consultant, OneSpin; and Jim Hogan, Board Director, OneSpin
How does a PSS model get verified and who will create that model? What happens when models extend beyond the specification?
Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions architect for Cadence Design Systems; and Tom Anderson, technical marketing consultant for OneSpin Solutions. What follows are excerpts of that conversation.
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Anderson: This is certainly an example of the way in which verification will influence design. You are playing with a level of parameters that affect what the hardware does. This is another dimension of the general problem.
By Brian Bailey, Semiconductor Engineering | Feat. Sven Beyer, Product Manager Design Verification, OneSpin
Pre-characterized tiles can move Moore’s Law forward, but it’s not as easy as it looks.
Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent ‘chiplet’ market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness.
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"The chiplet also offers more opportunities for both security vulnerabilities and hidden hardware Trojans," cautions Sven Beyer, product manager for design verification at OneSpin Solutions. "Integrators will expect the vendor to verify these aspects of integrity. The SoC team may wish to re-run some aspects of standalone IP verification as part of screening vendors and evaluating chiplets."
By Chris Edwards, Tech Design Forum | Feat. Dominik Strasser, VP Engineering, OneSpin
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OneSpin’s work found that solver orchestration based on machine learning is effective. The company is armed with more than two decades worth of collected designs that extend as far back as the team’s original work at Siemens in the early 1990s.
Dominik Strasser, vice president of engineering at OneSpin, says with the machine-learning functions: “Users do not normally have to pick proof algorithms and we now have a system that has faster proofs for time-to-hold,” adding that time-to-fail has rarely been an issue.
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As part of its ongoing work into applying AI to formal, a new project at OneSpin is aimed at helping with the debug process. “The tool finds out which part is the culprit. This is a very difficult problem to solve and a task for the future but we have some intermediate results. But don’t hold your breath,” Strasser says.
Another path OneSpin aims to pursue is using deep learning to analyse verification data. “Maybe then the runtime prediction will get better results,” Strasser hopes.
The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, today welcomed its newly elected 10-member Governing Council who will serve a two-year term.
Returning Governing Council members are:
Dr. Aart de Geus, chairman and co-chief executive officer (co-CEO) of Synopsys, Inc.
Dean Drako, president and CEO at IC Manage
Dr. John Kibarian, president and CEO of PDF Solutions, Inc.
Dr. Walden C. Rhines, CEO Emeritus of Mentor, a Siemens business
Simon Segars, CEO at Arm
Lip-Bu Tan, CEO of Cadence Design Systems
New Governing Council members are Dr. Raik Brinkmann, president and CEO of OneSpin Solutions, Dr. Prakash Narain, president and CEO of Real Intent and David Dutton, CEO of Silvaco. Robert P. Smith, executive director of the ESD Alliance, is also a member of the council.
The Governing Council was elected by the ESD Alliance’s voting members during the voting period that ended May 3. The new chair will be elected at the first meeting of the Governing Council meeting Thursday, May 23.
By Brian Bailey, Semiconductor Engineering | Feat. Tobias Welp, Engineering Manager, OneSpin
Combining the flexibility of a FPGA with the performance and cost benefits of an SoC is pushing this technology well into the mainstream.
The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs.
Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they need to launch products they know will need frequent updating.
Field programmable gate arrays (FPGAs) traditionally were considered too expensive for most applications and often relegated to prototypes or providing a time-to-market advantage for emerging standards. But the economics are changing. Integrating a reprogrammable fabric into an SoC is increasingly seen as a viable and valuable option.
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Machine learning is adding some new requirements into products. “FPGA fabric may be added to SoCs to enable variations in the engines and processors with domain-specific instruction sets,” points out OneSpin’s Welp. “In some cases, it may be possible to map algorithms for machine learning and other key applications into hardware and later refine the design as the results improve.”
