Functional Safety: Art Or Science?
By Sergio Marchese, Semiconductor Engineering
Nowadays, most hardware development projects deploy functional verification flows that include UVM-based constrained-random testbenches and formal verification. High design complexity, tough budget constraints, and short time to market are the norm, not the exception. Advanced verification is a necessity for many engineering teams. In our increasingly connected world, where billions of IoT devices soon will be communicating to us and to each other, security rapidly is becoming a key concern.
In recent years, countless engineers worldwide had their daily tasks influenced by functional safety. The ISO 26262 standard has been key to bringing safety into the development processes of thousands of companies within the automotive supply chain. The level of awareness and progress made is immense.
However, after 10 years from the publication of the standard’s first draft, many semiconductor and IP providers still struggle to establish a mature, ISO 26262-compliant flow.
Engineers have a plethora of qualitative and quantitative approaches to choose from. Critical tasks are often carried out solely through expert judgement, and largely manual processes where the main supporting tools are nothing more than word processors and spreadsheets. The methodology applied changes hugely from company to company and project to project, depending on the expertise available, application domain, and target safety integrity level.