Data Sheets

OneSpin® 360 Assertion Results Integration

Integrating the coverage metrics from complementary verification solutions such as simulation and formal is a known challenge especially when these have to be integrated into the verification planners for tracking completeness of the overall verification task. OneSpin provides a new tool to allow integration of the results of formal assertion runs into the verification plan allowing the end user to be able to visualize the integrated coverage results from simulation and formal in their planner of choice. The end user has the freedom to integrate results from OneSpin with simulation coverage generated from Synopsys VCS, Aldec Riviera-PRO and Mentor Questa and back annotate the results into the verification plan keeping track of the overall progress.

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OneSpin® 360 EC-FPGA™

The OneSpin 360 EC-FPGA™ solution ensures that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce synthesis and optimization errors. It eliminates gate-level simulation, and finds corner-case design flow bugs. It supports all sequential synthesis optimizations including complex sequential retiming. 360 EC is in use at multiple companies, as an accuracy gold standard to test their design solutions.

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OneSpin® 360 Fault Injection App

OneSpin’s Fault Injection App (FIA) automates the definition and handling of fault injection scenarios, removing the need for ad hoc verification flows or environments, thereby cutting on engineering effort and promoting reusability across projects and teams.

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OneSpin® 360 DV-Inspect

360 DV-InspectTM automatically inspects the RTL code once it has been compiled, without the need for any testbench setup. This code inspection comprises structural and exhaustive formal analysis with interactive debugging, eliminating an extensive amount of early simulation and stimulus creation while identifying issues before they result in serious bugs. Thus, DV-Inspect lends itself as a sign-off criterion for handing off an RTL block to functional verification and integration into automated daily regression runs.

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OneSpin® 360 DV-SC

High-Level Synthesis (HLS) transforms algorithmic and potentially untimed design models often written in SystemC and C++ to fully timed Register Transfer Level (RTL) design blocks. The primary verification requirement is to allow thorough verification of algorithmic code prior to synthesis, in order to ensure that the abstract algorithm implementation is tested and fully optimized against the original specification, as well as avoiding long debug cycles.

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OneSpin® 360 DV-Verify

OneSpin 360 DV-VerifyTM extends DV- Inspect with coverage-driven Assertion- Based Verification (ABV). Many entry-level formal apps allow for assertion generation for specific problems without a need for deep formal knowledge. For AMBATM protocols, the Protocol Compliance Checking App allows for exhaustive verification of all protocol rules, including providing the needed protocol constraints and interesting cover points.

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