Download technical descriptions of OneSpin products and apps
OneSpin® 360 DV Connectivity XL App
OneSpin’s Connectivity XL App is the industry’s first and only solution for the efficient specification and formal verification of huge numbers of deep connections in multi-billion-gate chips. Modern, 7nm ASIC and FPGA SoCs include hundreds of thousands of IP and module instances, and complex pin multiplexing logic. Connection paths may involve thousands of signals. Engineers often need to specify and verify in excess of one million connections. Moreover, maintaining a connectivity specification through design revisions and derivative projects require excessive effort. Overall, this is a time-consuming, error-prone task not adequately supported by simulation-based techniques or traditional formal connectivity checking apps.
OneSpin® 360 DV Floating-Point Unit App
OneSpin’s Floating-Point Unit (FPU) App is the industry’s first and only solution for the formal verification of floatingpoint hardware compliant to the IEEE 754 standard. The FPU App includes a reliable, extensively tested model of floating-point arithmetic operations, optimized for formal analysis. Engineers can set up the app within minutes and uncover deep, obscure corner-case bugs with minimal effort. The proven ability of the FPU App to find bugs even on already verified production designs is testament to its maturity, effectiveness, and unprecedented exhaustive coverage of floating-point arithmetic operands.
OneSpin® 360 DV-Inspect™
360 DV-Inspect automatically inspects RTL code once it has been compiled, without the need for any test bench setup. This code inspection comprises AutoLint and exhaustive formal analysis with interactive debugging, eliminating an extensive amount of early simulation and stimulus creation while identifying issues before they result in serious bugs. Thus, DV-Inspect lends itself as a sign-off criterion for handing off an RTL block to functional verification and integration into automated daily regression runs.
OneSpin® 360 DV-Verify™
OneSpin 360 DV-Verify adds coverage-driven assertion-based verification (ABV) to the DVInspect platform. It includes many entry-level formal apps that provide assertion generation for specific problems without a need for deep formal knowledge. For AMBATM protocols, formal VIPs allow for exhaustive verification of all protocol rules, including providing needed protocol constraints and interesting cover points. For register maps specified in formats such as IP-XACTTM, the CSR App exhaustive verifies that the RTL correctly implements the specified map. Data transport verification for blocks such as FIFOs or bus bridges can be highly automated with the Scoreboard App, efficiently finding any corruption in the data stream. The Connectivity App allows for fast chip-level connectivity analysis, and X-propagation issues can be automatically examined with the X-Prop App. The Verification Planning Integration App supports integration of the formal assertion results with verification planning tools, enabling a single verification plan for formal and simulationbased verification. The Verification Coverage Integration App supports combining metrics from formal and simulation.
OneSpin® 360 DV Verification Coverage Integration App
OneSpin’s VCI App enables users to export structural coverage results produced by OneSpin’s QuantifyTM in different database formats with a single command. Engineers can review formal and simulation coverage results side-by-side, identify coverage targets missed by both methods, and integrate results in a unified view.
OneSpin® 360 DV Verification Planning Integration App
In a systematic verification flow, requirements tracking and coverage play an indispensable role. Generally, this starts from requirements specification, where individual requirements are broken down into features, implementations, verification goals, and metrics. To achieve these goals, verification engineers take different approaches, such as writing testbenches for simulation or properties for assertion-based formal verification. Users generate coverage databases from simulation and formal environments to keep track of what requirements have been met. Because these metrics come from different vendors, the big challenge is how to merge these coverage databases into one and how to annotate the results into existing verification plans. OneSpin’s Verification Planning (VPI) App provides the solution.
OneSpin® 360 EC-FPGA™ Tool Qualification Kit (ISO 26262)
OneSpin 360 EC-FPGA is an automatic sequential equivalence checker that prevents field programmable gate array (FPGA) design flows from introducing synthesis, place-and-route and other implementation errors. Safety standards require rigorous verification before production to minimize the risk of failures in the field. With the most advanced formal technology, EC-FPGA detects corner-case design-flow bugs with a process that is orders of magnitude more efficient and rigorous than gate-level simulation. With this TÜV SÜD certified Tool Qualification Kit (TQK), users can deploy EC-FPGA seamlessly in their safety-critical flow to achieve a new level of productivity and standard compliance, without additional qualification effort.
OneSpin® 360 EC-FPGA™ Tool Assessment & Qualification Kits (DO-254)
OneSpin 360 EC-FPGA is an automatic sequential equivalence checker that prevents field programmable gate array (FPGA) design flows from introducing synthesis, place-and-route, and other implementation errors. Safety standards require rigorous verification before production to minimize the risk of failures in the field. With the most advanced formal technology, EC-FPGA detects corner-case design-flow bugs with a process that is orders of magnitude more efficient and rigorous than gate-level simulation. With this DER-reviewed Tool Qualification Kit (TQK), users can deploy EC-FPGA seamlessly in their DO-254 projects to achieve a new level of productivity and standard compliance, including for Design Assurance Level (DAL) A/B applications.
OneSpin® 360 EC-FPGA™
The OneSpin 360 EC-FPGA solution ensures that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce synthesis and optimization errors. It eliminates gate-level simulation and finds corner-case design flow bugs. It supports all sequential synthesis optimizations including complex sequential retiming. 360 EC is in use at multiple companies, as an accuracy gold standard to test their design solutions.
OneSpin® 360 Fault Injection Automation App™
OneSpin’s Fault Injection Automation (FIA) App automates the definition and handling of fault injection scenarios. This removes the need for ad hoc verification flows or environments, thereby reducing engineering effort and promoting reusability across projects and teams. The FIA App provides a simple and flexible interface to define any fault scenario, starting with the signals that shall be considered as candidates for fault injection, with no need to change the design or go through code-instrumentation steps.
OneSpin® 360 Fault Propagation Analysis App™
OneSpin’s Fault Propagation Analysis (FPA) App automatically identifies non-propagatable faults, allowing their safe elimination before pre- and post-simulation, thereby reducing simulation and debug time while increasing the nominal fault coverage. The FPA App uses dedicated formal algorithms and has two highly automated modes requiring minimal user intervention: fast mode and deep mode.
OneSpin® 360 DV Quantify™ App
OneSpin’s Quantify measures the quality of a formal verification test bench. It provides precise, actionable information on what parts of the design-under-test (DUT) are verified, and it highlights RTL code that could still hide bugs. Additionally, Quantify reveals potential issues in the test bench that might corrupt metrics and give a false sense of confidence.
OneSpin® 360 SystemC/C++ Extension™
High-level synthesis (HLS) transforms algorithmic and potentially untimed design models, often written in SystemC and C++, to fully timed register transfer level (RTL) design blocks. The primary verification requirement is enabling thorough verification of algorithmic code prior to synthesis, in order to ensure that the abstract algorithm implementation is tested and fully optimized against the original specification, while avoiding long debug cycles.