Our flyers provide a high-level overview around our solutions
OneSpin® 360 Design Verification Solutions
The OneSpin 360 Design Verification (DV) product line leverages the most advanced, high-performance formal technology as the basis for a range of verification solutions, from automated design analysis to advanced property checking. Solutions and apps have intuitive, flexible user interfaces and debug capabilities. They are easy to integrate into existing hardware development flows.
OneSpin® 360 EC-FPGA™
The OneSpin 360 EC-FPGA solution ensures that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce functional errors. It supports all sequential synthesis optimizations performed in FPGA design flows. OneSpin 360 EC-FPGA is in use at multiple companies as an accuracy gold standard to test their design solutions.
OneSpin® 360 Safety Verification Solution
Fault-tolerant electronic components in safety-critical systems are now commonplace in many industry sectors, including automotive, aerospace, power generation, defense, and medical. To guarantee the safe operation of SoCs under harsh environmental conditions, safety mechanisms are integrated to ensure a reliable, deterministic reaction to random hardware faults. ISO 26262 and other functional safety standards demand a quantitative analysis of random faults and their outcomes, and require a high ratio of detected, or safe, faults to all faults. This is hard to achieve with simulation-based fault injection alone, as certain faults, such as non-propagatable ones, are difficult to classify. In addition, to avoid systematic faults, such as RTL bugs or synthesis errors, these standards also demand a rigorous development process, with the careful tracking of requirements, from definition to test results and associated verification coverage metrics. Again, simulation alone cannot deliver the required level of verification quality, as a huge number of faults and input stimuli scenarios must be examined.
OneSpin® 360 SystemC/C++ Solution
Simulation-style verification of SystemC high-level synthesis (HLS) code is largely performed by compiling and debugging the design representation linked with a SystemC class library, in a similar fashion to a software test. Due to the limited availability of SystemC verification tools, much of the verification task is performed on the resulting synthesized RTL code, introducing a level of indirection that makes correcting issues complex and time consuming.