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DO-254 – Formal Verification Solutions for AEH

This presentation focuses on the formal verification solutions that can provide high ROI in AEH development projects. These solutions reduce the risk of undetected hardware issues, and enable a more predictable and efficient path to airworthiness certification.

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Formal Verification Applied to the Renesas MCU Design Platform Using the OneSpin Tools

Due to the wide range of different MCU types that are developed within a series of Renesas MCU’s in order to satisfy different applications we have developed the MCU-PF platform for both design and verification of a complete series of MCUs. A key issue is the effective verification for a combination of multiple IP components -this presents a significant task. Renesas developed the capability to use a Formal method of verification that provides full coverage of combinations of assertions while delivering significant reductions in both testing and verification time. Additional efficiency has been gained because the IP-Assertions are fully reusable along with the IP itself. This paper explains the methodology, its advantages and performance results compared to the simulation verification method.

Renesas is using the 360 DV-Certify product.

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From Requirements to Sign-off using Quantify

As chip design complexity continues to grow and the application of these chips diversifies from desktop and mobile platforms to automotive, avionics to IoT – this poses a unique mesh of challenges for validation and verification for safety, security, power and performance. The increased use of formal verification across the semiconductor industry over the last two decades is a testament to the fact that formal is about possibilities. Its application in safety verification, security verification, low-power validation and performance verification demonstrates the tremendous potential of the technology.

Download the presentation From Requirements to Sign-off using Quantify