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Verification Hygiene
Formal Verification with OneSpin

Design Verification Is All About Good Hygiene

By Ashish Darbari, Axiomise and Vladislav Palfy, OneSpin Solutions

Design verification has a lot in common with human hygiene practices. The goal of both activities is to remove all dirt, grime, and bugs through an active process of establishing good hygiene. If this process is not followed properly, the result is viruses, infections, and other illnesses. Good verification hygiene is as important in semiconductor development as human hygiene is for a healthy body.

This white paper discusses the different stages of verification hygiene and what kind of issues can be detected and corrected at each stage. Any design change requires it to be sanitized to eliminate any bugs introduced. A rinsing phase can detect more serious problems, while a deep scrub of the design removes corner-case bugs.

Finally, the detox phase validates assumptions and measures the coverage to ensure verification completeness. With this four-step process, design and verification engineers can release their chip bug- free and ensure that it conforms to the requirements.

The white paper covers the following design verification hygiene phases:

The sanitize phase of the flow begins as soon as you have a working copy of a design. The design could be in VHDL, Verilog or SystemC. The design itself may have been derived from a clearly written set of requirements or specifications, but it is not mandatory that one has a clear set of specifications and requirements for this phase to be exercised. Leveraging autochecks, code reachability analysis, initialization checks, and other automated verification steps that do not required a testbench, the sanitize phase checks design build quality to see if it is well-formed.

In the rinsing phase you need a bit more than just the design itself. The most important requirement at this stage is providing interface constraints for your design to enable a deeper formal analysis. Engineers may needs an understanding of user requirements and specifications. Largely automated formal checks run during this phase include deadlock and livelock checking, FSM analysis, X-Propagation, and detection of over-constraints through coverage analysis.

The previous two phases that have been described use mostly automatic features in a formal tool. In the scrub phase, the DV engineer is going a lot deeper in verification with the intent of flushing out bugs. This phase is about ensuring that the design conforms to the specification, hence the role of requirements and well-defined specifications is significant. Engineers shall have a verification strategy and plan, methodology to develop assertions and address complexity issues, and technology to compute accurate coverage metrics.

In the detox phase of the verification it is important to establish that the verification that was flagged as being of good quality in the previous phases (sanitize, rinse, and scrub) does not have any hidden toxins (bugs) anywhere. Engineers need tools and methodology to check that all user-defined constraints that yielded a 100% covered report are indeed legitimate constraints. Moreover, results shall be integrated in the overall verification plan. This is critical since it provides a holistic view on combining the results of running formal as well as other verification technologies such as simulation (directed testing and constrained-random).

Download the design verification white paper

Download the paper and learn about the four phases of the design verification (DV) hygiene flow.