close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

In the news

Bare Metal Programming

Semiconductor Engineering logo

As the need for safety and security grows across application areas such as automotive, industrial, and in the cloud, the semiconductor industry is searching for the best ways to protect these systems. The big question is whether it is better to build security and safety into hardware, into software, or both.

[…]

Read more



Seven Steps for IoT Verification

By Tom Anderson, Elektronikpraxis

Many IoT devices are complex system-on-chip (SoC) designs with embedded software. The development isn't trivial, and the verification is critical for successful deployments in end products.

[…]

Read more

The Impact Of Domain Crossing On Safety

Semiconductor Engineering logo

By Brian Bailey, Semiconductor Engineering

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications engineering, scientist for Synopsys. Part one can be found here. Part two is here. What follows are excerpts of that discussion.

[…]

Read more

The Impact Of Moore’s Law Ending

Semiconductor Engineering logo

By Brian Bailey, Semiconductor Engineering

Over the past couple of process nodes the chip industry has come to grips with the fact that Moore’s Law is slowing down or ending for many market segments. What isn’t clear is what comes next, because even if chipmakers stay at older nodes they will face a series of new challenges that will drive up costs and increase design complexity.

[…]

Read more

EDA Cloud Adoption Hits Speed Bumps

Semiconductor Engineering logo

By Brian Bailey, Semiconductor Engineering

popularity

If moving semiconductor design to the Cloud was easy and beneficial, everyone would be doing it. But so far, few have done more than dip a toe. The level of difficulty associated with migrating to the Cloud varies, depending upon who you talk to. The reality is that not everyone makes it as easy as it could be, or is not willing to put the necessary effort into making it easier. There is certainly a chicken-and-egg problem.

[…]

Read more

Integrating Results And Coverage From Simulation And Formal

Semiconductor Engineering logo

By Tom Anderson, Semiconductor Engineering

Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation licenses, and servers. Yet even unlimited simulation capability provided no guarantee of functional correctness. Constrained-random simulation, by its very nature, is probabilistic and has little chance of exercising enough of the design to find deep, corner-case bugs.

[…]

Read more

Press Contact

Michelle Clancy
» send an e-mail
» +1 503-702-4732