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In the news

More Sigmas In Auto Chips

Semiconductor Engineering logo

Ann Steffora-Mutschler, Semiconductor Engineering

The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems.

This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these devices, because they have to be designed in the context of other systems. Some of those systems are still deep in the development phase.

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Why Parallelization Is So Hard

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By Brain Bailey, Semiconductor Engineering

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for Oski Technology; and Bill Mullen, senior director for R&D at ANSYS. What follows are excerpts of that conversation.

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Pros, Cons Of ML-Specific Chips

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By Brain Bailey, Semiconductor Engineering

Machine Learning’s Limits, part 3: Which processor type is the best for training and inferencing, and why are there so many companies trying to build new processors specifically for machine learning and AI?

Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation.

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Functional Safety: Art Or Science?

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By Sergio Marchese, Semiconductor Engineering

Nowadays, most hardware development projects deploy functional verification flows that include UVM-based constrained-random testbenches and formal verification. High design complexity, tough budget constraints, and short time to market are the norm, not the exception. Advanced verification is a necessity for many engineering teams. In our increasingly connected world, where billions of IoT devices soon will be communicating to us and to each other, security rapidly is becoming a key concern.

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When Bugs Escape

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By Brian Bailey, Semiconductor Engineering

Bugs are a fact of life, and they always have been. But verification methodologies may not have evolved fast enough to keep up with the growing size and complexity of systems.

The types of bugs are changing, too. Some people call these corner cases. Others call them outliers. Still another group refers to them as simulation-resistance superbugs.

In markets such as automotive, the notion of bugs is evolving. Designs must be resilient not only to random faults, but must also be able to detect and recover from systemic faults, as well.

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Debug Issues Grow At New Nodes

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By Ann Steffora-Mutschler, Semiconductor Engineering

Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages.

The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it’s difficult to keep track of all the changes and potential interactions. Some blocks are “on” sometimes, some are “on” all the time, and some of them are sharing resources in ways that are difficult to understand. In effect, there is a combinatorial explosion of quasi-independent subsystems, and each of those blocks interacting with the others creates a different set of opportunities for misunderstandings, miscommunication, and a slew of other problems.

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Verification As A Flow I Part 3

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By Brian Bailey, Semiconductor Engineering

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verification Group at Cadence; and Roger Sabbagh, vice president of applications engineering for Oski Technology. What follows are excerpts of that conversation.

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Nicolas's Recipe for Digital Marketing in EDA

Paul McLellan, Breakfast Bytes

This is the third (and final) post about the ESD Alliance workshop on digital marketing in EDA. The first two were Digital Marketing in EDA...with No Hands on the Wheel, and ESD Alliance Workshop on Digital Marketing. Here is Nicolas's detailed recipe for a successful digital marketing campaign.

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