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OneSpin will formally unveil its formal RISC-V Integrity Verification Solution for development and assessment of the open-source IP at DVCon next week (Doubletree Hotel, San Jose, February 25-28). The company is exhibiting at Booth #301. The product will also be on view at EmbeddedWorld in Nuremberg on eVision System's booth (Hall 4, Booth 4-560).
By Ann Steffora-Mutschler, Semiconductor Engineering
Artificial intelligence is migrating from the cloud to IoT edge devices. Now the question is how to apply that same technology to protect data and identify abnormal activity in those devices and the systems connected to them.
Funktionale Verifikation von IoT Chips. Um zuverlässig IoT-Produkte entwicklen zu können, ist eine umfassende Verifikation der Chips vonnöten. Abkürzungen können zu schwerwiegenden Fehlern führen, die sich beim Anwender nur mit großem Aufwand beheben lassen.
Formal verification has traditionally been regarded as an advanced technique for experts to thoroughly verify individual blocks of logic, or perhaps small clusters of blocks. However, if you talk to anyone involved in the field these days, you’ll find that the majority of formal users are running applications (“apps”) targeted for specific verification problems. Further, many of these apps, notably connectivity checking, are being run at the full-chip level on very large designs. We’d like to use this month’s post to explore the links between these two extremes, looking at what has changed and what is likely to happen going forward.
With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle the pressures that artificial intelligence, automation and security put on systems. But how long will this sweet spot last for EDA?
Artificial intelligence is emerging as the driving force behind many advancements in technology, even though the industry has merely scratched the surface of what may be possible.
By Ann Steffora-Mutschler, Semiconductor Engineering
Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address problems much earlier than in the past.
Market segments such as cryptocurrencies and virtual reality are not living up to expectations, the market for smart phones appears to be saturated, and DRAM prices are dropping, leading to cut-backs in capital expenditures. EDA companies are talking about sales to China being put on hold in the shadow of a trade war between the United States and China. And there appears to be a slowdown in consumer electronics, as evidenced by Apple’s recent earnings and guidance.