close By using this website, you agree to the use of cookies. Detailed information on the use of cookies on this website can be obtained on OneSpin's Privacy Policy. At this point you may also object to the use of cookies and adjust the browser settings accordingly.

FPGA Implementation Verification

Verification of FPGA implementations for functional confidence with schedule and QoR improvements

FPGAs make use of a static hardware matrix, where the ratio of registers to inter-register logic is somewhat fixed. To drive the highest quality designs, state-of-the-art automated design flows, leveraging aggressive optimizations are employed. The combination of these optimizations on a varied range of Register Transfer Level (RTL) code styles can lead to the introduction of “systematic” errors. These errors can occur in unexpected ways, are often time consuming to detect, and potentially destructive.

OneSpin’s FPGA Implementation Verification Solution prevents these problems by applying formal verification to FPGA synthesis. This allows for the highest confidence in design operation, while also improving the development schedule and QoR.

FPGA Implementation Verification

To date, the standard way to find FPGA implementation errors is heavy regression testing on the FPGA itself, with thorough testing that examines every possible operational scenario. This requires many days of stimulus creation and execution, with no guarantee of RTL to gate equivalence.

In addition, if an issue is identified, it is hard to pinpoint the root cause of the problem, due to limited debug visibility in the FPGA device. Finally, after eliminating the problem, the process has to start again, involving time-consuming re-synthesis, and the same heavy regression testing. Specifically, for large FPGA devices, or when safety critical applications are targeted, this can lead to an unbearable burden on the design schedule.

Formal Verification for FPGA Synthesis

Equivalence Checking is commonly used for ASIC design, but to date this has not been possible in FPGAs due to the nature of the sequential optimizations employed. The OneSpin 360 Equivalence Checker, EC-FPGA is ideally suited for FPGA design. Its unique ability to handle retimed FPGA designs makes it an effective tool to track down systematic errors in the synthesis and P&R design flow. This solution is being used by the larger FPGA vendors to test their own synthesis tools, and supports major FPGA synthesis flows.

 

Applying OneSpin’s FPGA Implementation Verification solution provides the following benefits:

  • Confidence that all systematic issues have been eliminated, accelerating the test and debug process
  • Elimination of complex test creation or the need to predict systematic error fault conditions.
  • Confidence that no systematic-based corner case bugs exist in the final design, increasing reliability
  • Leveraging the most aggressive optimizations available, leading to power, speed and utilization improvements.

More information…


360 EC-FPGA is an automatic sequential equivalence checking tool that provides a fast and efficient method to ensure that aggressive synthesis optimizations have not introduced systematic errors that could disrupt the final design.

»Learn more about 360 EC-FPGA…

Muhammad Haque Khan, product specialist for Synthesis Verification, is speaking about our FPGA-specific, mature formal verification technology, that is exhaustive and efficient, catching many issues before synthesis starts.

»Watch the video now…

The OneSpin 360 EC-FPGA solution ensures that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce functional errors.

»Download the flyer…

The OneSpin 360 EC-FPGA™ solution ensures that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce synthesis and optimization errors.

»Download the data sheet…

OneSpin® 360 EC-FPGATM is an automatic sequential equivalence checker that prevents field programmable gate array (FPGA) design flows from introducing synthesis, place-and-route and other implementation errors.

»Download the data sheet…

This white paper presents an implementation signoff flow proving that the final FPGA netlist is functionally equivalent to the RTL model. Based on FPGA-specific, mature formal verification technology, the solution is exhaustive and efficient, catching many issues before synthesis starts.

»Download the white paper…

This case study demonstrates the value of EC in a real design scenario, by discussing the use of the technology by a design team to save time and reduce risk in a complex communications design.

»Read the case study…

This paper examines the reasons why the prevention of systematic errors become a major concern in this emerging application, and the new breed of EC technology required to fulfill this need.

»Read the paper…

“The MicroSemi ProASIC3 FPGA is a core component of the Advanced Logic System (ALS), and use of the OneSpin 360 Equivalence Checker is an integral part of our FPGA development process for nuclear safety systems.” says Erik Matusek, Safety System Platform Manager at Westinghouse Electric Company, LLC

»Read more…

"Logic Equivalency Checking (LEC) is a new feature supported with the Intel HyperFlex FPGA Architecture in Intel Quartus Prime Pro Edition software v17.1. It proves that the post Intel HyperFlex FPGA Architecture-optimized netlist is equivalent to the post fitter netlist. A third-party tool that you can refer to is the 360-EC FPGA solution by OneSpin."

»Read more…